On Tue, Mar 06, 2018 at 09:21:06AM +, Andre Przywara wrote:
> Our irq_is_pending() helper function accesses multiple members of the
> vgic_irq struct, so we need to hold the lock when calling it.
For the record I don't think this is necessarily a completely valid
conclusion. The fact that you
On Sun, Mar 11, 2018 at 12:49:56PM +, Marc Zyngier wrote:
> On guest exit, and when using GICv2 on GICv3, we use a dsb(st) to
> force synchronization between the memory-mapped guest view and
> the system-register view that the hypervisor uses.
>
> This is incorrect, as the spec calls out the n
On Sun, Mar 11, 2018 at 12:49:55PM +, Marc Zyngier wrote:
> The vgic code is trying to be clever when injecting GICv2 SGIs,
> and will happily populate LRs with the same interrupt number if
> they come from multiple vcpus (after all, they are distinct
> interrupt sources).
>
> Unfortunately, t
Hi James,
On 12/03/18 18:27, James Morse wrote:
> Hi Marc,
>
> On 01/03/18 15:55, Marc Zyngier wrote:
>> So far, the branch from the vector slots to the main vectors can at
>> most be 4GB from the main vectors (the reach of ADRP), and this
>> distance is known at compile time. If we were to remap
Hi Marc,
On 01/03/18 15:55, Marc Zyngier wrote:
> So far, the branch from the vector slots to the main vectors can at
> most be 4GB from the main vectors (the reach of ADRP), and this
> distance is known at compile time. If we were to remap the slots
> to an unrelated VA, things would break badly.
On 01/03/18 15:55, Marc Zyngier wrote:
> We lack a way to encode operations such as AND, ORR, EOR that take
> an immediate value. Doing so is quite involved, and is all about
> reverse engineering the decoding algorithm described in the
> pseudocode function DecodeBitMasks().
>
> This has been tes
On 09/03/18 18:59, James Morse wrote:
> Hi Marc,
>
> On 01/03/18 15:55, Marc Zyngier wrote:
>> We're now ready to map our vectors in weird and wonderful locations.
>> On enabling ARM64_HARDEN_EL2_VECTORS, a vector slots gets allocated
>> if this hasn't been already done via ARM64_HARDEN_BRANCH_PRE
[+Kristina for the extended idmap stuff]
Hi James,
On 09/03/18 18:59, James Morse wrote:
> Hi Marc,
>
> On 01/03/18 15:55, Marc Zyngier wrote:
>> We so far mapped our HYP IO (which is essencially the GICv2 control
>
> (Nit: essentially)
>
>
>> registers) using the same method as for memory. I
On 12/03/18 02:33, Yang, Shunyong wrote:
> Hi, Marc,
>
> On Sun, 2018-03-11 at 12:17 +, Marc Zyngier wrote:
>> On Sun, 11 Mar 2018 01:55:08 +
>> Christoffer Dall wrote:
>>
>>>
>>> On Sat, Mar 10, 2018 at 12:20 PM, Marc Zyngier >> m> wrote:
On Fri, 09 Mar 2018 21:36:12 +,
>>>