Re: [PATCH v2 00/17] arm64 SSBD (aka Spectre-v4) mitigation

2018-05-31 Thread Marc Zyngier
Hi Catalin, On 31/05/18 17:41, Catalin Marinas wrote: > On Tue, May 29, 2018 at 01:11:04PM +0100, Marc Zyngier wrote: >> Marc Zyngier (17): >> arm/arm64: smccc: Add SMCCC-specific return codes >> arm64: Call ARCH_WORKAROUND_2 on transitions between EL0 and EL1 >> arm64: Add per-cpu

Re: [PATCH v2 00/17] arm64 SSBD (aka Spectre-v4) mitigation

2018-05-31 Thread Catalin Marinas
On Tue, May 29, 2018 at 01:11:04PM +0100, Marc Zyngier wrote: > Marc Zyngier (17): > arm/arm64: smccc: Add SMCCC-specific return codes > arm64: Call ARCH_WORKAROUND_2 on transitions between EL0 and EL1 > arm64: Add per-cpu infrastructure to call ARCH_WORKAROUND_2 > arm64: Add

Re: [PATCH v2 2/6] arm64: KVM: Handle Set/Way CMOs as NOPs if FWB is present

2018-05-31 Thread Mark Rutland
On Thu, May 31, 2018 at 02:00:11PM +0100, Marc Zyngier wrote: > On 31/05/18 12:51, Mark Rutland wrote: > > On Wed, May 30, 2018 at 01:47:02PM +0100, Marc Zyngier wrote: > >> Set/Way handling is one of the ugliest corners of KVM. We shouldn't > >> have to handle that, but better safe than sorry. >

Re: [PATCH v2 2/6] arm64: KVM: Handle Set/Way CMOs as NOPs if FWB is present

2018-05-31 Thread Marc Zyngier
On 31/05/18 12:51, Mark Rutland wrote: > On Wed, May 30, 2018 at 01:47:02PM +0100, Marc Zyngier wrote: >> Set/Way handling is one of the ugliest corners of KVM. We shouldn't >> have to handle that, but better safe than sorry. >> >> Thankfully, FWB fixes this for us by not requiering any

Re: [PATCH v2 1/6] arm64: KVM: Add support for Stage-2 control of memory types and cacheability

2018-05-31 Thread Marc Zyngier
On 31/05/18 12:49, Mark Rutland wrote: > On Wed, May 30, 2018 at 01:47:01PM +0100, Marc Zyngier wrote: >> Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes >> results in the strongest attribute of the two stages. This means >> that the hypervisor has to perform quite a lot of cache

Re: [PATCH v2 6/6] KVM: arm/arm64: Remove unnecessary CMOs when creating HYP page tables

2018-05-31 Thread Mark Rutland
On Wed, May 30, 2018 at 01:47:06PM +0100, Marc Zyngier wrote: > There is no need to perform cache maintenance operations when > creating the HYP page tables if we have the multiprocessing > extensions. ARMv7 mandates them with the virtualization support, > and ARMv8 just mandates them

Re: [PATCH v2 5/6] KVM: arm/arm64: Stop using {pmd,pud,pgd}_populate

2018-05-31 Thread Mark Rutland
On Wed, May 30, 2018 at 01:47:05PM +0100, Marc Zyngier wrote: > The {pmd,pud,pgd}_populate accessors usage in the kernel have always > been a bit weird in KVM. We don't have a struct mm to pass (and > neither does the kernel most of the time, but still...), and > the 32bit code has all kind of

Re: [PATCH v2 4/6] KVM: arm/arm64: Consolidate page-table accessors

2018-05-31 Thread Mark Rutland
On Wed, May 30, 2018 at 01:47:04PM +0100, Marc Zyngier wrote: > The arm and arm64 KVM page tables accessors are pointlessly different > between the two architectures, and likely both wrong one way or another: > arm64 lacks a dsb(), and arm doesn't use WRITE_ONCE. > > Let's unify them. > >

Re: [PATCH v2 3/6] arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set

2018-05-31 Thread Mark Rutland
On Wed, May 30, 2018 at 01:47:03PM +0100, Marc Zyngier wrote: > On systems where CTR_EL0.DIC is set, we don't need to perform > icache invalidation to guarantee that we'll fetch the right > instruction stream. > > This also means that taking a permission fault to invalidate the > icache is an

Re: [PATCH v2 2/6] arm64: KVM: Handle Set/Way CMOs as NOPs if FWB is present

2018-05-31 Thread Mark Rutland
On Wed, May 30, 2018 at 01:47:02PM +0100, Marc Zyngier wrote: > Set/Way handling is one of the ugliest corners of KVM. We shouldn't > have to handle that, but better safe than sorry. > > Thankfully, FWB fixes this for us by not requiering any maintenance > whatsoever, which means we don't have to

Re: [PATCH v2 1/6] arm64: KVM: Add support for Stage-2 control of memory types and cacheability

2018-05-31 Thread Mark Rutland
On Wed, May 30, 2018 at 01:47:01PM +0100, Marc Zyngier wrote: > Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes > results in the strongest attribute of the two stages. This means > that the hypervisor has to perform quite a lot of cache maintenance > just in case the guest has

Re: [PATCH v5 10/15] ARM: spectre-v2: warn about incorrect context switching functions

2018-05-31 Thread Russell King - ARM Linux
On Thu, May 31, 2018 at 11:07:18AM +0100, Marc Zyngier wrote: > > I notice that you haven't replied to some of the patches (7 and 8), > > which makes me think that you have an issue with them - and as tonight > > is likely the last linux-next before the merge window, we're basically > > out of

Re: [PATCH v5 10/15] ARM: spectre-v2: warn about incorrect context switching functions

2018-05-31 Thread Marc Zyngier
On 31/05/18 10:49, Russell King - ARM Linux wrote: > On Tue, May 29, 2018 at 06:02:28PM +0100, Marc Zyngier wrote: >> On Tue, 29 May 2018 15:55:01 +0100, >> Russell King wrote: >>> >>> Warn at error level if the context switching function is not what we >>> are expecting. This can happen with

Re: [PATCH v5 10/15] ARM: spectre-v2: warn about incorrect context switching functions

2018-05-31 Thread Russell King - ARM Linux
On Tue, May 29, 2018 at 06:02:28PM +0100, Marc Zyngier wrote: > On Tue, 29 May 2018 15:55:01 +0100, > Russell King wrote: > > > > Warn at error level if the context switching function is not what we > > are expecting. This can happen with big.Little systems, which we > > currently do not