This patch series address two Qemu issues:
- improper system clock frequency initialization
- lack of pause (virtsh suspend) time accounting
A simple test to reproduce the problem executes one or more instances
of the following command in the guest:
dd if=/dev/zero of=/dev/null &
and then p
Initialize the generic timer scale factor based on the counter frequency
register cntfrq_el0, and default to the current static value if necessary.
Signed-off-by: Bijan Mottahedeh
---
hw/arm/virt.c | 15 +++
target/arm/helper.c| 19 ---
target/arm/interna
Accumulate the total guest pause time and update the virtual counter
offset register accordingly in order to account for that time before
resuming the guest.
Signed-off-by: Bijan Mottahedeh
---
hw/intc/arm_gicv3_kvm.c | 39 +++
target/arm/cpu.h| 3 +++
On Mon, Nov 5, 2018 at 11:45 PM Christoffer Dall
wrote:
>
> On Fri, Nov 02, 2018 at 02:23:45PM -0700, Miriam Zimmerman wrote:
> > In researching KVM_REG_ARM_TIMER_CNT, I discovered your commit 4b7a6bf
> > ("target-arm: kvm: Differentiate registers based on write-back
> > levels"), which seems to l
Christoffer Dall writes:
> On Fri, Nov 02, 2018 at 02:23:45PM -0700, Miriam Zimmerman wrote:
>> In researching KVM_REG_ARM_TIMER_CNT, I discovered your commit 4b7a6bf
>> ("target-arm: kvm: Differentiate registers based on write-back
>> levels"), which seems to limit when the KVM_REG_ARM_TIMER_CN
On 06/11/2018 12:33, Christoffer Dall wrote:
In attempting to re-construct the logic for our stage 2 page table
layout I found the reaoning in the comment explaining how we calculate
nit: reasoning
the number of levels used for stage 2 page tables a bit backwards.
This commit attempts to
In attempting to re-construct the logic for our stage 2 page table
layout I found the reaoning in the comment explaining how we calculate
the number of levels used for stage 2 page tables a bit backwards.
This commit attempts to clarify the comment, to make it slightly easier
to read without havin
On Tue, Nov 06, 2018 at 12:13:18PM +, Suzuki K Poulose wrote:
>
>
> On 06/11/2018 11:45, Christoffer Dall wrote:
> >On Tue, Nov 06, 2018 at 09:52:59AM +, Suzuki K Poulose wrote:
> >>
> >>
> >>On 06/11/2018 08:42, Christoffer Dall wrote:
> >>>On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuk
On 06/11/2018 11:45, Christoffer Dall wrote:
On Tue, Nov 06, 2018 at 09:52:59AM +, Suzuki K Poulose wrote:
On 06/11/2018 08:42, Christoffer Dall wrote:
On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuki K Poulose wrote:
On 02/11/18 14:25, Christoffer Dall wrote:
On Fri, Nov 02, 2018
On Tue, Nov 06, 2018 at 09:52:59AM +, Suzuki K Poulose wrote:
>
>
> On 06/11/2018 08:42, Christoffer Dall wrote:
> >On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuki K Poulose wrote:
> >>
> >>
> >>On 02/11/18 14:25, Christoffer Dall wrote:
> >>>On Fri, Nov 02, 2018 at 11:02:38AM +, Suzuki
On 06/11/2018 08:42, Christoffer Dall wrote:
On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuki K Poulose wrote:
On 02/11/18 14:25, Christoffer Dall wrote:
On Fri, Nov 02, 2018 at 11:02:38AM +, Suzuki K Poulose wrote:
Hi
On 02/11/18 07:53, Christoffer Dall wrote:
In attempting to re-c
On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuki K Poulose wrote:
>
>
> On 02/11/18 14:25, Christoffer Dall wrote:
> >On Fri, Nov 02, 2018 at 11:02:38AM +, Suzuki K Poulose wrote:
> >>Hi
> >>
> >>On 02/11/18 07:53, Christoffer Dall wrote:
> >>>In attempting to re-construct the logic for our s
On Mon, Nov 05, 2018 at 03:30:26PM +, Marc Zyngier wrote:
> We currently hide the LORegion feature, and generate an UNDEF
> if the guest dares using the corresponding registers. This is
> a bit extreme, as ARMv8.1 guarantees the feature to be present.
>
> The guest should check the feature reg
On Mon, Nov 05, 2018 at 02:36:16PM +, Marc Zyngier wrote:
> Early versions of Cortex-A76 can end-up with corrupt TLBs if they
> speculate an AT instruction in during a guest switch while the
> S1/S2 system registers are in an inconsistent state.
>
> Work around it by:
> - Mandating VHE
> - Mak
On Mon, Nov 05, 2018 at 02:36:15PM +, Marc Zyngier wrote:
> It is a bit odd that we only install stage-2 translation after having
> cleared HCR_EL2.TGE, which means that there is a window during which
> AT requests could fail as stage-2 is not configured yet.
>
> Let's move stage-2 configurati
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