From: Lan Tianyu
This patch is to register tlb_remote_flush_with_range callback with
hv tlb range flush interface.
Signed-off-by: Lan Tianyu
---
Change since v4:
- Use new function kvm_fill_hv_flush_list_func() to fill flush
request.
Change since v3:
- Merge Vitaly's don'
On Wed, Nov 07, 2018 at 10:22:06AM -0800, Miriam Zimmerman wrote:
> On Wed, Nov 7, 2018 at 1:42 AM Christoffer Dall
> wrote:
> >
> > On Tue, Nov 06, 2018 at 10:37:21AM -0800, Miriam Zimmerman wrote:
> > > On Mon, Nov 5, 2018 at 11:45 PM Christoffer Dall
> > > wrote:
> > > >
> > > > On Fri, Nov 02
On 07/11/18 21:59, Will Deacon wrote:
On Wed, Sep 26, 2018 at 02:56:22PM +0100, Julien Thierry wrote:
When an EL2 entry of __kvm_hyp_vector is taken, it means an entry from a
lower EL was previously taken to exit the guest. Taking that lower EL entry
already applied BP hardening if it was nee
Peter Maydell writes:
> On 7 November 2018 at 17:39, Peter Maydell wrote:
>> On 7 November 2018 at 17:10, Alex Bennée wrote:
>>> Not all faults handled by handle_exit are instruction emulations. For
>>> example a ESR_ELx_EC_IABT will result in the page tables being updated
>>> but the instruct
On 07/11/18 21:59, Will Deacon wrote:
On Wed, Sep 26, 2018 at 02:56:23PM +0100, Julien Thierry wrote:
When an EL2 entry of __kvm_hyp_vector is taken, it means an entry from a
lower EL was previously taken to exit the guest. Taking that lower EL entry
already applied vector hardening if needed
Mark Rutland writes:
> On Wed, Nov 07, 2018 at 06:01:20PM +, Mark Rutland wrote:
>> On Wed, Nov 07, 2018 at 05:10:31PM +, Alex Bennée wrote:
>> > Not all faults handled by handle_exit are instruction emulations. For
>> > example a ESR_ELx_EC_IABT will result in the page tables being upda
On Thu, Nov 08, 2018 at 12:40:11PM +, Alex Bennée wrote:
> Mark Rutland writes:
> > On Wed, Nov 07, 2018 at 06:01:20PM +, Mark Rutland wrote:
> >> On Wed, Nov 07, 2018 at 05:10:31PM +, Alex Bennée wrote:
> >> > Not all faults handled by handle_exit are instruction emulations. For
> >>
Mark Rutland writes:
> On Thu, Nov 08, 2018 at 12:40:11PM +, Alex Bennée wrote:
>> Mark Rutland writes:
>> > On Wed, Nov 07, 2018 at 06:01:20PM +, Mark Rutland wrote:
>> >> On Wed, Nov 07, 2018 at 05:10:31PM +, Alex Bennée wrote:
>> >> > Not all faults handled by handle_exit are ins
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1541616504-68526-1-git-send-email-bijan.mottahe...@oracle.com
Subject: [Qemu-devel] [RFC Q
Hi,
This series failed docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1541616504-68526-1-git-send-email-bijan.mottahe...@oracle.com
Subject: [Qemu-devel] [RFC
On 8 November 2018 at 14:28, Alex Bennée wrote:
>
> Mark Rutland writes:
>> One problem is that I couldn't spot when we advance the PC for an MMIO
>> trap. I presume we do that in the kernel, *after* the MMIO trap, but I
>> can't see where that happens.
>
> Nope it gets done before during decode_
Hi Jean-Philippe,
On 10/12/18 4:59 PM, Jean-Philippe Brucker wrote:
> When the device offers the probe feature, send a probe request for each
> device managed by the IOMMU. Extract RESV_MEM information. When we
> encounter a MSI doorbell region, set it up as a IOMMU_RESV_MSI region.
> This will te
Hi Jean-Philippe,
On 10/12/18 6:35 PM, Michael S. Tsirkin wrote:
> On Fri, Oct 12, 2018 at 03:59:15PM +0100, Jean-Philippe Brucker wrote:
>> The virtio IOMMU is a para-virtualized device, allowing to send IOMMU
>> requests such as map/unmap over virtio transport without emulating page
>> tables. T
On 11/7/18 7:48 PM, Bijan Mottahedeh wrote:
>
> +static void set_system_clock_scale(void)
> +{
> +unsigned long cntfrq_el0;
> +
> +asm volatile("mrs %0, cntfrq_el0" : "=r"(cntfrq_el0));
> +
> +if (cntfrq_el0 == 0) {
> +cntfrq_el0 = GTIMER_SCALE_DEF;
> +}
> +
> +system_
From: Lan Tianyu
Sorry. Some patches was blocked and I try to resend via another account.
For nested memory virtualization, Hyper-v doesn't set write-protect
L1 hypervisor EPT page directory and page table node to track changes
while it relies on guest to tell it changes via HvFlushGuestAddress
From: Lan Tianyu
This patch is to replace kvm_flush_remote_tlbs() with kvm_flush_
remote_tlbs_with_address() in some functions without logic change.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/mmu.c | 31 +--
arch/x86/kvm/paging_tmpl.h | 3 ++-
2 files chang
From: Lan Tianyu
This patch is to trace log in the hyperv_nested_flush_
guest_mapping_range().
Signed-off-by: Lan Tianyu
---
arch/x86/hyperv/nested.c| 1 +
arch/x86/include/asm/trace/hyperv.h | 14 ++
2 files changed, 15 insertions(+)
diff --git a/arch/x86/hyperv/nest
From: Lan Tianyu
This patch is to add wrapper functions for tlb_remote_flush_with_range
callback and flush tlb directly in kvm_mmu_zap_collapsible_spte().
kvm_mmu_zap_collapsible_spte() returns flush request to the
slot_handle_leaf() and the latter does flush on demand. When
range flush is availa
From: Lan Tianyu
Add flush range call back in the kvm_x86_ops and platform can use it
to register its associated function. The parameter "kvm_tlb_range"
accepts a single range and flush list which contains a list of ranges.
Signed-off-by: Lan Tianyu
---
Change since v1:
Change "end_gfn"
From: Lan Tianyu
The patch is to make kvm_set_spte_hva() return int and caller can
check return value to determine flush tlb or not.
Signed-off-by: Lan Tianyu
---
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/mips/include/asm/kvm_host.h| 2 +-
From: Lan Tianyu
This patch is to register tlb_remote_flush_with_range callback with
hv tlb range flush interface.
Signed-off-by: Lan Tianyu
---
Change since v4:
- Use new function kvm_fill_hv_flush_list_func() to fill flush
request.
Change since v3:
- Merge Vitaly's don'
From: Lan Tianyu
Hyper-V provides HvFlushGuestAddressList() hypercall to flush EPT tlb
with specified ranges. This patch is to add the hypercall support.
Reviewed-by: Michael Kelley
Signed-off-by: Lan Tianyu
---
Change sincd v4:
- Expose function hyperv_fill_flush_guest_mapping_list()
On 08/11/2018 10:26, Christoffer Dall wrote:
> On Wed, Nov 07, 2018 at 10:22:06AM -0800, Miriam Zimmerman wrote:
>> On Wed, Nov 7, 2018 at 1:42 AM Christoffer Dall
>> wrote:
>>>
>>> On Tue, Nov 06, 2018 at 10:37:21AM -0800, Miriam Zimmerman wrote:
On Mon, Nov 5, 2018 at 11:45 PM Christoffer D
On 08/11/2018 14:48, Auger Eric wrote:
>> +struct virtio_iommu_probe_property {
>> +__le16 type;
>> +__le16 length;
> the value[] field has disappeared but still is documented in the v0.8 spec.
Good catch. I removed value[]
On 08/11/2018 14:51, Auger Eric wrote:
>>> +/*
>>> + * viommu_replay_mappings - re-send MAP requests
>>> + *
>>> + * When reattaching a domain that was previously detached from all
>>> endpoints,
>>> + * mappings were deleted from the device. Re-create the mappings available
>>> in
>>> + * the in
On 05/11/18 18:34, James Morse wrote:
> Hi Marc,
>
> On 05/11/2018 14:36, Marc Zyngier wrote:
>> Early versions of Cortex-A76 can end-up with corrupt TLBs if they
>> speculate an AT instruction in during a guest switch while the
>
> (in during?)
>
>> S1/S2 system re
On 06/11/18 07:53, Christoffer Dall wrote:
> On Mon, Nov 05, 2018 at 02:36:14PM +, Marc Zyngier wrote:
>> Some implementations may be forced to use VHE to work around HW
>> errata, for example. Let's introduce a helper that checks for
>> these cases.
>>
>> Signed-off-by: Marc Zyngier
>> ---
>>
On 06/11/18 08:06, Christoffer Dall wrote:
> On Mon, Nov 05, 2018 at 02:36:15PM +, Marc Zyngier wrote:
>> It is a bit odd that we only install stage-2 translation after having
>> cleared HCR_EL2.TGE, which means that there is a window during which
>> AT requests could fail as stage-2 is not con
On 06/11/18 08:15, Christoffer Dall wrote:
> On Mon, Nov 05, 2018 at 02:36:16PM +, Marc Zyngier wrote:
>> Early versions of Cortex-A76 can end-up with corrupt TLBs if they
>> speculate an AT instruction in during a guest switch while the
>> S1/S2 system registers are in an inconsistent state.
>
On Tue, Nov 06, 2018 at 08:52:51AM +0100, Christoffer Dall wrote:
> On Mon, Nov 05, 2018 at 02:36:13PM +, Marc Zyngier wrote:
> > An SVE system is so far the only case where we mandate VHE. As we're
> > starting to grow this requirements, let's slightly rework the way we
> > deal with that situ
From: "Joel Fernandes (Google)"
Android needs to mremap large regions of memory during memory management
related operations. The mremap system call can be really slow if THP is
not enabled. The bottleneck is move_page_tables, which is copying each
pte at a time, and can be really slow across a la
From: "Joel Fernandes (Google)"
This series speeds up mremap(2) syscall by copying page tables at the
PMD level even for non-THP systems. There is concern that the extra
'address' argument that mremap passes to pte_alloc may do something
subtle architecture related in the future that may make the
Hi,
Here is the "fast mremap" series. This just a repost with Kirill's Acked-bys
added and William's Reviewed-by added. Also fixed a UML build error reported
last week. I would like this to be considered for linux -next. The performance
numbers in the series are for testing on x86. The config enabl
From: "Joel Fernandes (Google)"
Moving page-tables at the PMD-level on x86 is known to be safe. Enable
this option so that we can do fast mremap when possible.
Suggested-by: Kirill A. Shutemov
Acked-by: Kirill A. Shutemov
Signed-off-by: Joel Fernandes (Google)
---
arch/x86/Kconfig | 1 +
1 f
On Mon, Nov 05, 2018 at 02:36:14PM +, Marc Zyngier wrote:
> Some implementations may be forced to use VHE to work around HW
> errata, for example. Let's introduce a helper that checks for
> these cases.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm/include/asm/kvm_host.h | 1 +
> arch/a
On Thu, Nov 08, 2018 at 04:34:08PM +, Steven Price wrote:
> On 08/11/2018 10:26, Christoffer Dall wrote:
> > On Wed, Nov 07, 2018 at 10:22:06AM -0800, Miriam Zimmerman wrote:
> >> On Wed, Nov 7, 2018 at 1:42 AM Christoffer Dall
> >> wrote:
> >>>
> >>> On Tue, Nov 06, 2018 at 10:37:21AM -0800,
On Thu, Nov 08, 2018 at 06:05:55PM +, Marc Zyngier wrote:
> On 06/11/18 08:15, Christoffer Dall wrote:
> > On Mon, Nov 05, 2018 at 02:36:16PM +, Marc Zyngier wrote:
> >> Early versions of Cortex-A76 can end-up with corrupt TLBs if they
> >> speculate an AT instruction in during a guest swit
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