Re: [PATCH v7 05/23] iommu: Introduce cache_invalidate API

On Thu, 2 May 2019 11:53:34 +0100 Jean-Philippe Brucker wrote: > On 02/05/2019 07:58, Auger Eric wrote: > > Hi Jean-Philippe, > > > > On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote: > >> On 08/04/2019 13:18, Eric Auger wrote: > >>> +int iommu_cache_invalidate(struct iommu_domain *domain, st

Re: [PATCH AUTOSEL 5.0 29/98] KVM: arm/arm64: Enforce PTE mappings at stage2 when needed

On Tue, Apr 23, 2019 at 10:27:26AM +0100, Suzuki K Poulose wrote: Hi Sasha, On 04/22/2019 08:40 PM, Sasha Levin wrote: From: Suzuki K Poulose [ Upstream commit a80868f398554842b14d07060012c06efb57c456 ] commit 6794ad5443a2118 ("KVM: arm/arm64: Fix unintended stage 2 PMD mappings") made the c

Re: [PATCH v7 05/23] iommu: Introduce cache_invalidate API

On 02/05/2019 07:58, Auger Eric wrote: > Hi Jean-Philippe, > > On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote: >> On 08/04/2019 13:18, Eric Auger wrote: >>> +int iommu_cache_invalidate(struct iommu_domain *domain, struct device *dev, >>> + struct iommu_cache_invalidate_info *

Re: [PATCH v5 5/5] KVM: arm/arm64: support chained PMU counters

Hi Andrew, I have a few remarks. I don't think it's anything major, nor that the approach need to be changed. On 01/05/2019 17:31, Andrew Murray wrote: > ARMv8 provides support for chained PMU counters, where an event type > of 0x001E is set for odd-numbered counters, the event counter will > inc

Re: [PATCH] KVM: arm64: fix ptrauth ID register masking logic

On Wed, May 01, 2019 at 05:20:49PM +0100, Marc Zyngier wrote: > On 01/05/2019 17:10, Kristina Martsenko wrote: > > When a VCPU doesn't have pointer auth, we want to hide all four pointer > > auth ID register fields from the guest, not just one of them. > > > > Fixes: 384b40caa8af ("KVM: arm/arm64: