On 03-07-19, 18:42, Dave Martin wrote:
> From: Zhang Lei
>
> The original implementation of vq_present() relied on aggressive
> inlining in order for the compiler to know that the code is
> correct, due to some const-casting issues. This was causing sparse
> and clang to complain, while GCC comp
On Wed, Jul 03, 2019 at 12:04:11PM +, Zhang, Lei wrote:
> Hi guys,
>
> I can't start up KVM guest os with SVE feature with your patch.
> The error message is
> qemu-system-aarch64: kvm_init_vcpu failed: Invalid argument.
>
> My test enviroment.
> kernel linux-5.2-rc6
> qemu [Qemu-devel] [P
From: Zhang Lei
The original implementation of vq_present() relied on aggressive
inlining in order for the compiler to know that the code is
correct, due to some const-casting issues. This was causing sparse
and clang to complain, while GCC compiled cleanly.
Commit 0c529ff789bc addressed this p
Hi Julien,
On 20/06/2019 14:06, Julien Grall wrote:
> At the moment, the VMID algorithm will send an SGI to all the CPUs to
> force an exit and then broadcast a full TLB flush and I-Cache
> invalidation.
>
> This patch re-use the new ASID allocator. The
> benefits are:
> - CPUs are not forced
Hi Julien,
On 20/06/2019 14:06, Julien Grall wrote:
> Some users of the ASID allocator (e.g VMID) will require to update the
> context when a new ASID is generated. This has to be protected by a lock
> to prevent concurrent modification.
>
> Rather than introducing yet another lock, it is possibl
On 7/3/19 4:59 PM, Marc Zyngier wrote:
> On 25/06/2019 16:18, Alexandru Elisei wrote:
>> Hi Marc,
>>
>> A question regarding this patch. This patch modifies
>> vcpu_{read,write}_sys_reg
>> to handle virtual EL2 registers. However, the file kvm/emulate-nested.c
>> added by
>> patch 10/59 "KVM: a
On Wed, Jul 03, 2019 at 01:20:55PM +0100, Marc Zyngier wrote:
> On 24/06/2019 13:54, Dave Martin wrote:
> > On Fri, Jun 21, 2019 at 10:37:51AM +0100, Marc Zyngier wrote:
> >> From: Jintack Lim
> >>
> >> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
> >> this bit is set, a
On 26/06/2019 06:31, Julien Thierry wrote:
>
>
> On 06/21/2019 10:38 AM, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not
>> coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set.
>>
>> In addition to EL2 register a
On Wed, Jul 03, 2019 at 12:53:58PM +0100, Marc Zyngier wrote:
> On 24/06/2019 12:28, Dave Martin wrote:
> > On Fri, Jun 21, 2019 at 10:37:48AM +0100, Marc Zyngier wrote:
> >> From: Christoffer Dall
> >>
> >> Introduce the feature bit and a primitive that checks if the feature is
> >> set behind a
On Wed, Jul 03, 2019 at 12:56:51PM +0100, Marc Zyngier wrote:
> On 24/06/2019 12:43, Dave Martin wrote:
> > On Fri, Jun 21, 2019 at 10:37:48AM +0100, Marc Zyngier wrote:
> >> From: Christoffer Dall
> >>
> >> Introduce the feature bit and a primitive that checks if the feature is
> >> set behind a
On Wed, Jul 03, 2019 at 10:30:03AM +0100, Marc Zyngier wrote:
> On 24/06/2019 12:19, Dave Martin wrote:
> > On Fri, Jun 21, 2019 at 10:37:46AM +0100, Marc Zyngier wrote:
> >> Having __load_guest_stage2 in kvm_hyp.h is quickly going to trigger
> >> a circular include problem. In order to avoid this,
On 03/07/2019 14:20, Marc Zyngier wrote:
> On 24/06/2019 16:47, Alexandru Elisei wrote:
>> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>>> From: Jintack Lim
[...]
>>> + { SYS_DESC(SYS_VPIDR_EL2), access_rw, reset_val, VPIDR_EL2, 0 },
>>> + { SYS_DESC(SYS_VMPIDR_EL2), access_rw, reset_val, VMPID
On 25/06/2019 16:18, Alexandru Elisei wrote:
> Hi Marc,
>
> A question regarding this patch. This patch modifies vcpu_{read,write}_sys_reg
> to handle virtual EL2 registers. However, the file kvm/emulate-nested.c added
> by
> patch 10/59 "KVM: arm64: nv: Support virtual EL2 exceptions" already us
On 6/21/19 10:38 AM, Marc Zyngier wrote:
> As we are about to reuse our stage 2 page table manipulation code for
> shadow stage 2 page tables in the context of nested virtualization, we
> are going to manage multiple stage 2 page tables for a single VM.
>
> This requires some pretty invasive chang
On 03/07/2019 13:15, Marc Zyngier wrote:
> On 24/06/2019 13:42, Julien Thierry wrote:
>>
>>
>> On 06/21/2019 10:37 AM, Marc Zyngier wrote:
>>> From: Andre Przywara
>>>
>>> KVM internally uses accessor functions when reading or writing the
>>> guest's system registers. This takes care of accessi
On 25/06/2019 15:19, Julien Thierry wrote:
>
>
> On 06/21/2019 10:38 AM, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> Forward exceptions due to WFI or WFE instructions to the virtual EL2 if
>> they are not coming from the virtual EL2 and virtual HCR_EL2.TWX is set.
>>
>> Signed-off-by: Jintack
On 25/06/2019 14:13, Alexandru Elisei wrote:
> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> Now that the psci call is done by the smc instruction when nested
> This suggests that we have support for PSCI calls using SMC as the conduit,
> but
> that is not the case, as the h
On 25/06/2019 13:55, Julien Thierry wrote:
>
>
> On 06/21/2019 10:38 AM, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> When HCR.NV bit is set, execution of the EL2 translation regime address
>> aranslation instructions and TLB maintenance instructions are trapped to
>> EL2. In addition, executi
On 6/21/19 10:38 AM, Marc Zyngier wrote:
> From: Jintack Lim
>
> Exposing memory management support to the virtual EL2 as is exposed to
> the host hypervisor would make the implementation too complex and
> inefficient. Therefore expose limited memory management support for the
> following two ca
On 6/21/19 10:38 AM, Marc Zyngier wrote:
> We don't want to expose complicated features to guests until we have
> a good grasp on the basic CPU emulation. So let's pretend that RAS,
> just like SVE, doesn't exist in a nested guest.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/sys_regs
On 25/06/2019 13:19, Alexandru Elisei wrote:
> On 6/21/19 10:38 AM, Marc Zyngier wrote:
>> From: Christoffer Dall
>>
>> Add stage 2 mmu data structures for virtual EL2 and for nested guests.
>> We don't yet populate shadow stage 2 page tables, but we now have a
>> framework for getting to a shadow
On 25/06/2019 09:48, Julien Thierry wrote:
>
>
> On 06/21/2019 10:38 AM, Marc Zyngier wrote:
>> From: Andre Przywara
>>
>> Whenever we need to restore the guest's system registers to the CPU, we
>> now need to take care of the EL2 system registers as well. Most of them
>> are accessed via traps
On 24/06/2019 16:47, Alexandru Elisei wrote:
> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
>> this bit is set, accessing EL2 registers in EL1 traps to EL2. In
>> addition, executing the following instru
On 24/06/2019 16:07, Julien Thierry wrote:
>
>
> On 06/21/2019 10:37 AM, Marc Zyngier wrote:
>> Extract the direct HW accessors for later reuse.
>>
>> Signed-off-by: Marc Zyngier
>> ---
>> arch/arm64/kvm/sys_regs.c | 247 +-
>> 1 file changed, 139 insertions(
On 24/06/2019 13:59, Alexandru Elisei wrote:
> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>> From: Dave Martin
>>
>> Currently, the {read,write}_sysreg_el*() accessors for accessing
>> particular ELs' sysregs in the presence of VHE rely on some local
>> hacks and define their system register encodin
On 24/06/2019 13:54, Dave Martin wrote:
> On Fri, Jun 21, 2019 at 10:37:51AM +0100, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
>> this bit is set, accessing EL2 registers in EL1 traps to EL2. In
>> addition, executing the
On 24/06/2019 13:42, Julien Thierry wrote:
>
>
> On 06/21/2019 10:37 AM, Marc Zyngier wrote:
>> From: Andre Przywara
>>
>> KVM internally uses accessor functions when reading or writing the
>> guest's system registers. This takes care of accessing either the stored
>> copy or using the "live" EL
Hi guys,
I can't start up KVM guest os with SVE feature with your patch.
The error message is
qemu-system-aarch64: kvm_init_vcpu failed: Invalid argument.
My test enviroment.
kernel linux-5.2-rc6
qemu [Qemu-devel] [PATCH v2 00/14] target/arm/kvm: enable SVE in guests
https://lists.gnu.org/arc
On 24/06/2019 12:43, Dave Martin wrote:
> On Fri, Jun 21, 2019 at 10:37:48AM +0100, Marc Zyngier wrote:
>> From: Christoffer Dall
>>
>> Introduce the feature bit and a primitive that checks if the feature is
>> set behind a static key check based on the cpus_have_const_cap check.
>>
>> Checking ne
On 24/06/2019 12:28, Dave Martin wrote:
> On Fri, Jun 21, 2019 at 10:37:48AM +0100, Marc Zyngier wrote:
>> From: Christoffer Dall
>>
>> Introduce the feature bit and a primitive that checks if the feature is
>> set behind a static key check based on the cpus_have_const_cap check.
>>
>> Checking ne
On Wed, Jul 03, 2019 at 10:35:37AM +0100, Will Deacon wrote:
> On Fri, Jun 07, 2019 at 12:26:21PM +0100, Dave Martin wrote:
> > This series, based on kvmtool master [1], implements basic support for
> > pointer authentication and SVE for guests. This superseded the
> > previous v3 series [2].
>
>
On Fri, Jun 07, 2019 at 12:26:21PM +0100, Dave Martin wrote:
> This series, based on kvmtool master [1], implements basic support for
> pointer authentication and SVE for guests. This superseded the
> previous v3 series [2].
I'd prefer to use the release headers for 5.2, so I've taken the first t
On 24/06/2019 12:19, Dave Martin wrote:
> On Fri, Jun 21, 2019 at 10:37:46AM +0100, Marc Zyngier wrote:
>> Having __load_guest_stage2 in kvm_hyp.h is quickly going to trigger
>> a circular include problem. In order to avoid this, let's move
>> it to kvm_mmu.h, where it will be a better fit anyway.
On 24/06/2019 13:48, Dave Martin wrote:
> On Fri, Jun 21, 2019 at 02:50:08PM +0100, Marc Zyngier wrote:
>> On 21/06/2019 14:24, Julien Thierry wrote:
>>>
>>>
>>> On 21/06/2019 10:37, Marc Zyngier wrote:
From: Christoffer Dall
We were not allowing userspace to set a more privileged m
On 6/21/19 10:38 AM, Marc Zyngier wrote:
> From: Jintack Lim
>
> With HCR_EL2.NV bit set, accesses to EL12 registers in the virtual EL2
> trap to EL2. Handle those traps just like we do for EL1 registers.
>
> One exception is CNTKCTL_EL12. We don't trap on CNTKCTL_EL1 for non-VHE
> virtual EL2 b
On 7/2/19 5:32 PM, Alexandru Elisei wrote:
> On 6/21/19 10:38 AM, Marc Zyngier wrote:
>> From: Jintack Lim
>>
>> Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the
>> virtual HCR_EL2.NV bit is set.
> HCR_EL2.NV1?
>> This is for recursive nested virtualization.
>>
>> Signed-off
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