Hi Marc,
On 7/25/19 5:35 PM, Marc Zyngier wrote:
> From: Marc Zyngier
>
> In order to avoid leaking vgic_irq structures on teardown, we need to
> drop all references to LPIs before deallocating the cache itself.
>
> This is done by invalidating the cache on vgic teardown.
>
> Signed-off-by: Ma
Hi Marc,
On 7/25/19 5:35 PM, Marc Zyngier wrote:
> From: Marc Zyngier
>
> If a vcpu disables LPIs at its redistributor level, we need to make sure
> we won't pend more interrupts. For this, we need to invalidate the LPI
> translation cache.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Eric Aug
On Wed, Jul 24, 2019 at 05:25:28PM +0100, Julien Grall wrote:
> The function check_and_switch_context is used to:
> 1) Check whether the ASID is still valid
> 2) Generate a new one if it is not valid
> 3) Switch the context
>
> While the latter is specific to the MM subsystem, the rest
On 25/07/2019 11:01, Andre Przywara wrote:
> Thanks! Feel free to add my Tested-by: at an appropriate place.
Ah, sorry, missed that. If you give the new series a go, I swear I'll
add your tag! ;-)
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_
From: Marc Zyngier
Now that we have a cache of MSI->LPI translations, it is pretty
easy to implement kvm_arch_set_irq_inatomic (this cache can be
parsed without sleeping).
Hopefully, this will improve some LPI-heavy workloads.
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
virt/kvm/
From: Marc Zyngier
When performing an MSI injection, let's first check if the translation
is already in the cache. If so, let's inject it quickly without
going through the whole translation process.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 36 +
From: Marc Zyngier
In order to avoid leaking vgic_irq structures on teardown, we need to
drop all references to LPIs before deallocating the cache itself.
This is done by invalidating the cache on vgic teardown.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 2 ++
1 file chang
From: Marc Zyngier
If an ITS gets disabled, we need to make sure that further interrupts
won't hit in the cache. For that, we invalidate the translation cache
when the ITS is disabled.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --
From: Marc Zyngier
The LPI translation cache needs to be discarded when an ITS command
may affect the translation of an LPI (DISCARD, MAPC and MAPD with V=0)
or the routing of an LPI to a redistributor with disabled LPIs (MOVI,
MOVALL).
We decide to perform a full invalidation of the cache, irre
From: Marc Zyngier
If a vcpu disables LPIs at its redistributor level, we need to make sure
we won't pend more interrupts. For this, we need to invalidate the LPI
translation cache.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-mmio-v3.c | 4 +++-
1 file changed, 3 insertions(+), 1 de
From: Marc Zyngier
Add the basic data structure that expresses an MSI to LPI
translation as well as the allocation/release hooks.
The size of the cache is arbitrarily defined as 16*nr_vcpus.
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
include/kvm/arm_vgic.h| 3 +++
virt/
On 25.07.19 15:25, Andrew Jones wrote:
On Thu, Jul 25, 2019 at 03:09:49PM +0200, Alexander Graf wrote:
This patch adds a unit test for the PL031 RTC that is used in the virt machine.
It just pokes basic functionality. I've mostly written it to familiarize myself
with the device, but I suppose
On Thu, Jul 25, 2019 at 03:09:49PM +0200, Alexander Graf wrote:
> This patch adds a unit test for the PL031 RTC that is used in the virt
> machine.
> It just pokes basic functionality. I've mostly written it to familiarize
> myself
> with the device, but I suppose having the test around does not
On Thu, Jul 25, 2019 at 02:17:32PM +0200, Alexander Graf wrote:
> This patch adds a unit test for the PL031 RTC that is used in the virt
> machine.
> It just pokes basic functionality. I've mostly written it to familiarize
> myself
> with the device, but I suppose having the test around does not
Hi,
On 13/07/2019 05:40, Zenghui Yu wrote:
> We've added two ESR exception classes for new ARM hardware extensions:
> ESR_ELx_EC_PAC and ESR_ELx_EC_SVE.
>
> This patch updates "kvm_arm_exception_class" for these two EC, which the
> new EC will be parsed in kvm_exit trace events (for guest's usag
On Thu, Jul 25, 2019 at 02:12:19PM +0200, Alexander Graf wrote:
>
>
> On 15.07.19 18:42, Andrew Jones wrote:
> > On Fri, Jul 12, 2019 at 11:19:38AM +0200, Alexander Graf wrote:
> > > This patch adds a unit test for the PL031 RTC that is used in the virt
> > > machine.
> > > It just pokes basic f
On Thu, 25 Jul 2019 09:50:18 +0100
Marc Zyngier wrote:
Hi Marc,
> On 23/07/2019 12:14, Andre Przywara wrote:
> > On Tue, 11 Jun 2019 18:03:27 +0100
> > Marc Zyngier wrote:
> >
> > Hi,
> >
> >> It recently became apparent[1] that our LPI injection path is not as
> >> efficient as it could be
Hi Andre,
On 23/07/2019 12:14, Andre Przywara wrote:
> On Tue, 11 Jun 2019 18:03:27 +0100
> Marc Zyngier wrote:
>
> Hi,
>
>> It recently became apparent[1] that our LPI injection path is not as
>> efficient as it could be when injecting interrupts coming from a VFIO
>> assigned device.
>>
>> Al
On 23/07/2019 16:14, Auger Eric wrote:
> Hi Marc,
>
> On 6/11/19 7:03 PM, Marc Zyngier wrote:
>> Now that we have a cache of MSI->LPI translations, it is pretty
>> easy to implement kvm_arch_set_irq_inatomic (this cache can be
>> parsed without sleeping).
>>
>> Hopefully, this will improve some LP
19 matches
Mail list logo
