On 2019-12-02 16:56, Richard Henderson wrote:
On 12/2/19 4:45 PM, Marc Zyngier wrote:
Annoying that there's a bug in the manual -- FPSID is listed as
group 0 in
plenty of places, except in the pseudo-code for Accessing the FPSID
which uses TID3.
Are you sure? I'm looking at DDI0487E_a,
...
On 12/2/19 4:45 PM, Marc Zyngier wrote:
>> Annoying that there's a bug in the manual -- FPSID is listed as group 0 in
>> plenty of places, except in the pseudo-code for Accessing the FPSID
>> which uses TID3.
>
> Are you sure? I'm looking at DDI0487E_a,
...
> Or have you spotted a discrepancy
> so
On 2019-12-02 15:35, Richard Henderson wrote:
On 12/1/19 12:20 PM, Marc Zyngier wrote:
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these c
On 12/1/19 12:20 PM, Marc Zyngier wrote:
> +if (cpu_isar_feature(jazelle, cpu)) {
> +ARMCPRegInfo jazelle_regs[] = {
static const.
Otherwise,
Reviewed-by: Richard Henderson
r~
___
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://
On 12/1/19 12:20 PM, Marc Zyngier wrote:
> +/* Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
> + * to sysregs non accessible at EL0 to have UNDEF-ed already.
> + */
We're enforcing
/*
* Multi-line comment
*/
for qemu now; checkpatch should be reporting o
On 12/1/19 12:20 PM, Marc Zyngier wrote:
> HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
> In order to handle this, introduce a new TCG helper function that
> checks for these control bits before executing the VMRC ins
On 12/1/19 12:20 PM, Marc Zyngier wrote:
> HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
> (and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
> to EL2. QEMU ignores it, making it harder for a hypervisor to
> virtualize the HW (though to be fair, no known hypervis
On 12/1/19 12:20 PM, Marc Zyngier wrote:
> HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
> CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
> completely ignores it, making it impossible for hypervisors to
> virtualize the cache hierarchy.
>
> Do the right thing
On Sun, Dec 01, 2019 at 12:20:18PM +, Marc Zyngier wrote:
> QEMU lacks the minimum Jazelle implementation that is required
> by the architecture (everything is RAZ or RAZ/WI). Add it
> together with the HCR_EL2.TID0 trapping that goes with it.
Looks good to me:
Reviewed-by: Edgar E. Iglesias
On Sun, Dec 01, 2019 at 12:20:14PM +, Marc Zyngier wrote:
> HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
> CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
> completely ignores it, making it impossible for hypervisors to
> virtualize the cache hierarchy.
>
10 matches
Mail list logo
