From: Eric Auger
Triggers LPIs through the INT command.
the test checks the LPI hits the right CPU and triggers
the right LPI intid, ie. the translation is correct.
Updates to the config table also are tested, along with inv
and invall commands.
Signed-off-by: Eric Auger
Reviewed-by: Zenghui
From: Eric Auger
Introduce an helper functions to register
- a new device, characterized by its device id and the
max number of event IDs that dimension its ITT (Interrupt
Translation Table). The function allocates the ITT.
- a new collection, characterized by its ID and the
target
From: Eric Auger
Add two new migration tests. One testing the migration of
a topology where collection were unmapped. The second test
checks the migration of the pending table.
Signed-off-by: Eric Auger
[ Complete migration even when the test is skipped. Otherwise the
migration scripts hang.
From: Eric Auger
Implement main ITS commands. The code is largely inherited from
the ITS driver.
Signed-off-by: Eric Auger
Reviewed-by: Zenghui Yu
Signed-off-by: Andrew Jones
---
arm/Makefile.arm64 | 2 +-
lib/arm64/asm/gic-v3-its.h | 55 +
lib/arm64/gic-v3-its-cmd.c | 459
From: Eric Auger
PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management.
Signed-off-by: Eric Auger
Reviewed-by: Zenghui Yu
Signed-off-by: Andrew Jones
---
lib/arm/asm/gic-v3.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
From: Eric Auger
Let's link getchar.o to use puts and getchar from the
tests.
Then allow tests belonging to the migration group to
trigger the migration from the test code by putting
"migrate" into the uart. Then the code can wait for the
migration completion by using getchar().
The __getchar
From: Eric Auger
This test maps LPIs (populates the device table, the collection table,
interrupt translation tables, configuration table), migrates and make
sure the translation is correct on the destination.
Signed-off-by: Eric Auger
Reviewed-by: Zenghui Yu
[ Complete migration even when
From: Eric Auger
its_enable_defaults() enable LPIs at redistributor level
and ITS level.
gicv3_enable_defaults must be called before.
Signed-off-by: Eric Auger
Reviewed-by: Zenghui Yu
Signed-off-by: Andrew Jones
---
lib/arm/asm/gic-v3.h | 6 ++
lib/arm/gic-v3.c | 25
From: Eric Auger
Allocate the LPI configuration and per re-distributor pending table.
Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
by default in the config table.
Also introduce a helper routine that allows to set the pending
table bit for a given LPI and macros to set/get
From: Eric Auger
Adds the following tests:
- event-counter-config: test event counter configuration
- basic-event-count:
- programs counters #0 and #1 to count 2 required events
(resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset
to a value close enough to the 32b
overflow limit so
From: Eric Auger
Allows to set or clear the enable state of a PPI/SGI/SPI.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/gic.h | 4
lib/arm/gic.c | 31 +++
2 files changed, 35 insertions(+)
diff --git a/lib/arm/asm/gic.h
From: Eric Auger
As we intend to introduce more PMU tests, let's add
a sub-test parameter that will allow to categorize
them. Existing tests are in the cycle-counter category.
Signed-off-by: Eric Auger
Reviewed-by: Andre Przywara
Signed-off-by: Andrew Jones
---
arm/pmu.c | 25
From: Eric Auger
Add 2 tests exercising chained counters. The first one uses
CPU_CYCLES and the second one uses SW_INCR.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
arm/pmu.c | 98 ++-
arm/unittests.cfg | 12 ++
2 files
From: Eric Auger
check_pmcr() checks the IMP field is different than 0.
However A zero IMP field is permitted by the architecture,
meaning the MIDR_EL1 should be looked at instead. This
causes TCG to fail this test on '-cpu max' because in
that case PMCR.IMP is set equal to MIDR_EL1.Implementer
Sometimes we need to test access to system registers which are
missing assembler mnemonics.
Signed-off-by: Andrew Jones
Reviewed-by: Alexandru Elisei
---
lib/arm64/asm/sysreg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h
From: Eric Auger
If event counters are implemented check the common events
required by the PMUv3 are implemented.
Some are unconditionally required (SW_INCR, CPU_CYCLES,
either INST_RETIRED or INST_SPEC). Some others only are
required if the implementation implements some other features.
Check
From: Eric Auger
Add tests dedicated to SW_INCR event counting.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
arm/pmu.c | 47 +++
arm/unittests.cfg | 6 ++
2 files changed, 53 insertions(+)
diff --git a/arm/pmu.c
From: Eric Auger
Test configurations where we transit from 32b to 64b
counters and conversely. Also tests configuration where
chain counters are configured but only one counter is
enabled.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
arm/pmu.c | 138
From: Eric Auger
Detect the presence of an ITS as part of the GICv3 init
routine, initialize its base address and read few registers
the IIDR, the TYPER to store its dimensioning parameters.
Parse the BASER registers. As part of the init sequence we
also init all the requested tables.
This is
From: Eric Auger
Introduce some defines encoding the different PMU versions.
v3 is encoded differently in 32 and 64 bits.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
arm/pmu.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git
From: Eric Auger
Test overflows for MEM_ACCESS and SW_INCR events. Also tests
overflows with 64-bit events.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
arm/pmu.c | 139 ++
arm/unittests.cfg | 6 ++
2 files changed, 145
From: Eric Auger
Introduce additional SZ_256, SZ_8K, SZ_16K macros that will
be used by ITS tests.
Signed-off-by: Eric Auger
Reviewed-by: Thomas Huth
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index
From: Eric Auger
ipi_enable() code would be reusable for other interrupts
than IPI. Let's rename it setup_irq() and pass an interrupt
handler pointer.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
arm/gic.c | 19 ++-
lib/arm/asm/processor.h | 2 ++
From: Eric Auger
Compute the power of 2 order of a size. Use it in
page_memalign. Other users are looming.
Signed-off-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/alloc_page.c | 7 ++-
lib/alloc_page.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git
From: Zenghui Yu
We already have some good helpers to access the counter and timer
registers. Use them to avoid open coding the accessors again.
Signed-off-by: Zenghui Yu
Signed-off-by: Andrew Jones
---
arm/timer.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
Let's bail out of the wait loop if we see the expected state
to save over six seconds of run time. Make sure we wait a bit
before reading the registers and double check again after,
though, to somewhat mitigate the chance of seeing the expected
state by accident.
We also take this opportunity to
From: Eric Auger
This struct aims at storing information potentially used by
all tests such as the pmu version, the read-only part of the
PMCR, the number of implemented event counters, ...
Signed-off-by: Eric Auger
Reviewed-by: Andre Przywara
Signed-off-by: Andrew Jones
---
arm/pmu.c | 29
From: Zenghui Yu
The status of each interrupt are defined by the GIC architecture and
maintained by GIC hardware. They're not specified to the timer HW.
Let's move this software enumeration to a more proper place.
Signed-off-by: Zenghui Yu
Signed-off-by: Andrew Jones
---
arm/timer.c |
From: Alexandru Elisei
When the timer is disabled (the *_CTL_EL0.ENABLE bit is clear) or the
timer interrupt is masked at the timer level (the *_CTL_EL0.IMASK bit is
set), timer interrupts must not be pending or asserted by the VGIC.
However, only when the timer interrupt is masked, we can still
From: Alexandru Elisei
When the MMU is off, data accesses are to Device nGnRnE memory on arm64 [1]
or to Strongly-Ordered memory on arm [2]. This means that the accesses are
non-cacheable.
Perform a dcache clean to PoC so we can read the newer values from the
cache after we turn the MMU off,
From: Alexandru Elisei
>From ARM DDI 0487E.a glossary, the section "Context synchronization
event":
"All direct and indirect writes to System registers that are made before
the Context synchronization event affect any instruction, including a
direct read, that appears in program order after the
From: Zenghui Yu
We're actually going to read GICR_ISACTIVER0 and GICR_ISPENDR0 (in
SGI_base frame of the redistribitor) to get the active/pending state
of the timer interrupt. Fix this typo.
And since they have the same value, there's no functional change.
Signed-off-by: Zenghui Yu
From: Alexandru Elisei
We check that the interrupt is pending (or not) at the GIC level, but we
don't check if the timer is asserting it (or not). Let's make sure we don't
run into a strange situation where the two devices' states aren't
synchronized.
Coincidently, the "interrupt signal no
From: Alexandru Elisei
Let's fix the typos so that the -fno-stack-protector and
-fno-stack-protector-all compiler options are actually used.
Tested by compiling for arm64, x86_64 and ppc64 little endian. Before the
patch, the arguments were missing from the gcc invocation; after the patch,
they
From: Alexandru Elisei
The psci test performs a series of CPU_ON/CPU_OFF cycles for CPU 1. This is
done by setting the entry point for the CPU_ON call to the physical address
of the C function cpu_psci_cpu_die.
The compiler is well within its rights to use the stack when generating
code for
From: Alexandru Elisei
Writing to the EOIR register before masking the HW mapped timer
interrupt can cause taking another timer interrupt immediately after
exception return. This doesn't happen all the time, because KVM
reevaluates the state of pending HW mapped level sensitive interrupts on
From: Alexandru Elisei
There is a delay between the timer asserting the interrupt and the GIC
sampling the interrupt state. Let's take that into account when we are
checking if the timer interrupt is pending (or not) at the GIC level.
An interrupt can be pending or active and pending [1,2].
From: Alexandru Elisei
The irq_received field is modified by the interrupt handler. Make it
volatile so that the compiler doesn't reorder accesses with regard to
the instruction that will be causing the interrupt.
Suggested-by: Andre Przywara
Signed-off-by: Alexandru Elisei
Signed-off-by:
Hi Paolo,
This pull request is a repost of an older request, plus it
contains Eric's new PMU and ITS tests.
Thanks,
drew
The following changes since commit ce27fa2c7cd4d07859a9a2e81c7ff641897818d1:
x86: vmx: skip atomic_switch_overflow_msrs_test on bare metal (2020-03-31
13:01:41 -0400)
From: Alexandru Elisei
Reads of the physical counter and the virtual counter registers "can occur
speculatively and out of order relative to other instructions executed on
the same PE" [1, 2].
There is no theoretical limit to the number of instructions that the CPU
can reorder and we use the
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