Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes

On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: > This series is primarily motivated from an adhoc list from Mark Rutland > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > which does macro replacement for various open bits shift encodings in > various CPU

Re: I{S,C}ACTIVER implemention question

Hi Julien, Thanks for the heads up. On 2020-04-06 14:16, Julien Grall wrote: Hi, Xen community is currently reviewing a new implementation for reading I{S,C}ACTIVER registers (see [1]). The implementation is based on vgic_mmio_read_active() in KVM, i.e the active state of the interrupts is ba

[PATCH] KVM: arm64: arch_timer shouldn't assume the vcpu is loaded

kvm_arch_timer_get_input_level() needs to get the arch_timer_context for a particular vcpu, and uses kvm_get_running_vcpu() to find it. kvm_arch_timer_get_input_level() may be called to handle a user-space write to the redistributor, where the vcpu is not loaded. This causes kvm_get_running_vcpu()

I{S,C}ACTIVER implemention question

Hi, Xen community is currently reviewing a new implementation for reading I{S,C}ACTIVER registers (see [1]). The implementation is based on vgic_mmio_read_active() in KVM, i.e the active state of the interrupts is based on the vGIC state stored in memory. While reviewing the patch on xen-de