On Mon, Jul 06, 2020 at 01:54:08PM +0100, Marc Zyngier wrote:
> Catalin: How do you want to proceed for patches 2, 3, and 4? I could
> make a stable branch that gets you pull into the arm64 tree, or the
> other way around. Just let me know.
Please create a separate branch for the S2 TTL patches (i
On Mon, Jul 06, 2020 at 01:54:11PM +0100, Marc Zyngier wrote:
> Advertise bits [58:55] as reserved for SW in the S2 descriptors.
>
> Reviewed-by: Andrew Scull
> Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
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On Mon, Jul 06, 2020 at 01:54:12PM +0100, Marc Zyngier wrote:
> Add a level-hinted TLB invalidation helper that only gets used if
> ARMv8.4-TTL gets detected.
>
> Reviewed-by: Alexandru Elisei
> Signed-off-by: Marc Zyngier
Same here:
Reviewed-by: Catalin Marinas
__
On Mon, Jul 06, 2020 at 01:54:10PM +0100, Marc Zyngier wrote:
> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> feature allows TLBs to be issued with a level allowing for quicker
> invalidation.
>
> Let's detect the feature for now. Further patches will implement
> its actual us
On 06/07/20 13:05, Marc Zyngier wrote:
> git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git
> tags/kvmarm-fixes-5.8-3
Pulled, thanks.
Paolo
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Hi Marc,
On 7/6/20 1:17 PM, Marc Zyngier wrote:
> On 2020-06-25 13:19, Alexandru Elisei wrote:
>> Hi Marc,
>>
>> On 6/16/20 5:18 PM, Marc Zyngier wrote:
>>> Hi Alexandru,
>>> [..]
> [..]
>
> /**
> - * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
> - *
HVC_SOFT_RESTART is given values for x0-2 that it should installed
before exiting to the new address so should not set x0 to stub HVC
success or failure code.
Signed-off-by: Andrew Scull
---
arch/arm64/kvm/hyp-init.S | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a
As part of the ongoing spring cleanup, remove the now useless
vcpu parameter that is passed around (host and guest contexts
give us everything we need).
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/include/hyp/debug-sr.h | 18 --
1 file changed, 8 insertions(+), 10 deletion
As we're about to move SPSR_EL1 into the VNCR page, we need to
disassociate it from the rest of the 32bit cruft. Let's break
the array into individual fields.
Reviewed-by: James Morse
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_emulate.h | 4 +--
arch/arm64/include/asm/kvm
SP_EL1 being a VNCR-capable register with ARMv8.4-NV, move it to the
system register array and update the accessors.
Reviewed-by: James Morse
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_host.h | 3 +--
arch/arm64/kvm/guest.c | 2 +-
arch/arm64/kvm/hyp
struct kvm_regs is used by userspace to indicate which register gets
accessed by the {GET,SET}_ONE_REG API. But as we're about to refactor
the layout of the in-kernel register structures, we need the kernel to
move away from it.
Let's make kvm_regs userspace only, and let the kernel map it to its
Move the timer gsisters to the sysreg file. This will further help when
they are directly changed by a nesting hypervisor in the VNCR page.
This requires moving the initialisation of the timer struct so that some
of the helpers (such as arch_timer_ctx_index) can work correctly at an
early stage.
Now that we have a wrapper for the sysreg accesses, let's use that
consistently.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/fpsimd.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c
index e329a36b2bee..e503caff14d1 10064
From: Christoffer Dall
As we are about to reuse our stage 2 page table manipulation code for
shadow stage 2 page tables in the context of nested virtualization, we
are going to manage multiple stage 2 page tables for a single VM.
This requires some pretty invasive changes to our data structures,
SPSR_EL1 being a VNCR-capable register with ARMv8.4-NV, move it to
the sysregs array and update the accessors.
Reviewed-by: James Morse
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_emulate.h | 4 ++--
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/kvm/guest.c
As ELR-EL1 is a VNCR-capable register with ARMv8.4-NV, let's move it to
the sys_regs array and repaint the accessors. While we're at it, let's
kill the now useless accessors used only on the fault injection path.
Reviewed-by: James Morse
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kv
kvm_timer_sync_hwstate() has nothing to do with the timer HW state,
but more to do with the state of a userspace interrupt controller.
Change the suffix from _hwstate to_user, in keeping with the rest
of the code.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/arch_timer.c | 2 +-
arch/arm64/kv
Advertise bits [58:55] as reserved for SW in the S2 descriptors.
Reviewed-by: Andrew Scull
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/pgtable-hwdef.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
b/arch/arm64/include/asm/pgtable-hwdef.
Hi all,
In order not to repeat the 90+ patch series that resulted in a
deafening silence last time, I've extracted a smaller set of patches
that form the required dependencies that allow the rest of the 65 NV
patches to be added on top. Yes, it is that bad.
The one real feature here is support fo
Since we often have a precise idea of the level we're dealing with
when invalidating TLBs, we can provide it to as a hint to our
invalidation helper.
Reviewed-by: James Morse
Reviewed-by: Alexandru Elisei
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_asm.h | 3 ++-
arch/arm64/kvm
Now that we have a wrapper for the sysreg accesses, let's use that
consistently.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/include/hyp/switch.h | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h
b/arch/a
Switch the hypervisor code to using ctxt_sys_reg/__vcpu_sys_reg instead
of raw sys_regs accesses. No intended functionnal change.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/kvm/hyp/include/hyp/debug-sr.h | 4 +-
arch/arm64/kvm/hyp/include/h
In order to allow the disintegration of the per-vcpu sysreg array,
let's introduce a new helper (ctxt_sys_reg()) that returns the
in-memory copy of a system register, picked from a given context.
__vcpu_sys_reg() is rewritten to use this helper.
Signed-off-by: Marc Zyngier
---
arch/arm64/includ
In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
feature allows TLBs to be issued with a level allowing for quicker
invalidation.
Let's detect the feature for now. Further patches will implement
its actual usage.
Reviewed-by : Suzuki K Polose
Signed-off-by: Marc Zyngier
---
arc
Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.
Reviewed-by: Alexandru Elisei
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/stage2_pgtable.h | 9 +
arch/arm64/include/asm/tlbflush.h | 45 +
2 files changed,
Hi Marc,
On 7/6/20 1:15 PM, Marc Zyngier wrote:
> Hi Alex,
>
> On 2020-06-26 16:39, Alexandru Elisei wrote:
>> Hi,
>>
>> On 6/15/20 2:27 PM, Marc Zyngier wrote:
>>> In order to allow the disintegration of the per-vcpu sysreg array,
>>> let's introduce a new helper (ctxt_sys_reg()) that returns the
Hi Eric,
On 7/3/2020 3:45 PM, Auger Eric wrote:
Hi Jingyi,
On 7/3/20 9:41 AM, Jingyi Wang wrote:
Hi Eric, Drew,
On 7/2/2020 9:36 PM, Auger Eric wrote:
Hi Jingyi,
On 7/2/20 5:01 AM, Jingyi Wang wrote:
Trigger PPIs by setting up a 10msec timer and test the latency.
so for each iteration th
On 2020-06-25 13:19, Alexandru Elisei wrote:
Hi Marc,
On 6/16/20 5:18 PM, Marc Zyngier wrote:
Hi Alexandru,
[..]
[..]
/**
- * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2
translation.
- * @kvm: The KVM struct pointer for the VM.
+ * kvm_init_stage2_mmu - Initialise a S2 MMU
Hi Alex,
On 2020-06-26 16:39, Alexandru Elisei wrote:
Hi,
On 6/15/20 2:27 PM, Marc Zyngier wrote:
In order to allow the disintegration of the per-vcpu sysreg array,
let's introduce a new helper (ctxt_sys_reg()) that returns the
in-memory copy of a system register, picked from a given context.
Hi Paolo,
Yet another small batch of fixes for 5.8. One is a long standing
preemption issue that got uncovered by another fix that went in
5.8. The other one is a fix for an issue potentially affecting kexec.
Please pull,
M.
The following changes since commit a3f574cd65487cd993f79ab235d
Commit 07da1ffaa137 ("KVM: arm64: Remove host_cpu_context
member from vcpu structure") has, by removing the host CPU
context pointer, exposed that kvm_vcpu_pmu_restore_guest
is called in preemptible contexts:
[ 266.932442] BUG: using smp_processor_id() in preemptible [] code:
qemu-system
From: Andrew Scull
HVC_SOFT_RESTART is given values for x0-2 that it should installed
before exiting to the new address so should not set x0 to stub HVC
success or failure code.
Fixes: af42f20480bf1 ("arm64: hyp-stub: Zero x0 on successful stub handling")
Cc: sta...@vger.kernel.org
Signed-off-by
On Mon, 6 Jul 2020 10:52:59 +0100, Andrew Scull wrote:
> HVC_SOFT_RESTART is given values for x0-2 that it should installed
> before exiting to the new address so should not set x0 to stub HVC
> success or failure code.
Applied to kvm-arm64/fixes-5.8-3, thanks!
[1/1] KVM: arm64: Stop clobbering x
On 2020-07-06 10:52, Andrew Scull wrote:
HVC_SOFT_RESTART is given values for x0-2 that it should installed
before exiting to the new address so should not set x0 to stub HVC
success or failure code.
Signed-off-by: Andrew Scull
---
arch/arm64/kvm/hyp-init.S | 11 +++
1 file changed, 7
Hi Keqian,
On 2020-07-06 02:28, zhukeqian wrote:
Hi Catalin and Marc,
On 2020/7/2 21:55, Keqian Zhu wrote:
This patch series add support for dirty log based on HW DBM.
It works well under some migration test cases, including VM with 4K
pages or 2M THP. I checked the SHA256 hash digest of all
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