Hi Will,
On Mon, Mar 8, 2021 at 10:49 AM Will Deacon wrote:
>
> On Fri, Feb 05, 2021 at 04:44:03AM +, Jing Zhang wrote:
> > Remove redundant check for CPU feature S2FWB in dcache flush code
> > to save some CPU cycles for every memslot flush and unmapping.
> > And move the S2FWB check to
On Fri, Mar 05, 2021 at 12:21:24PM -0800, Sami Tolvanen wrote:
> allmodconfig + CONFIG_LTO_CLANG_THIN=y fails to build due to following
> linker errors:
>
> ld.lld: error: irqbypass.c:(function __guest_enter: .text+0x21CC):
> relocation R_AARCH64_CONDBR19 out of range: 2031220 is not in
>
Hi Alex,
On Mon, 08 Mar 2021 16:53:09 +,
Alexandru Elisei wrote:
>
> Hello,
>
> It's not clear to me why this patch is needed. If one VCPU in the VM is
> generating
> code, is it not the software running in the VM responsible for keeping track
> of
> the MMU state of the other VCPUs and
Hi Jean,
On 3/5/21 11:45 AM, Jean-Philippe Brucker wrote:
> Hi,
>
> On Tue, Feb 23, 2021 at 10:06:15PM +0100, Eric Auger wrote:
>> This patch adds the VFIO_IOMMU_SET_MSI_BINDING ioctl which aim
>> to (un)register the guest MSI binding to the host. This latter
>> then can use those stage 1
KVM/arm64 has forever used a 40bit default IPA space, partially
due to its 32bit heritage (where the only choice is 40bit).
However, there are implementations in the wild that have a *cough*
much smaller *cough* IPA space, which leads to a misprogramming of
VTCR_EL2, and a guest that is stuck on
On Monday 08 Mar 2021 at 12:46:07 (+), Will Deacon wrote:
> __load_stage2() _only_ has the ISB if ARM64_WORKAROUND_SPECULATIVE_AT is
> present, whereas I think you need one unconditionall here so that the
> system register write has taken effect before the TLB invalidation.
>
> It's similar
Hi Andre,
On 2/25/21 12:59 AM, Andre Przywara wrote:
> Now that the PC keyboard has a trap handler adhering to the MMIO fault
> handler prototype, let's switch over to the joint registration routine.
>
> This allows us to get rid of the ioport shim routines.
>
> Make the kbd_init() function
Hi Andre,
On 2/25/21 12:58 AM, Andre Przywara wrote:
> With the planned retirement of the special ioport emulation code, we
> need to provide an emulation function compatible with the MMIO
> prototype.
>
> Adjust the trap handler to use that new function, and provide shims to
> implement the old
Hello,
It's not clear to me why this patch is needed. If one VCPU in the VM is
generating
code, is it not the software running in the VM responsible for keeping track of
the MMU state of the other VCPUs and making sure the new code is executed
correctly? Why should KVM get involved?
I don't see
On Fri, Feb 05, 2021 at 04:44:03AM +, Jing Zhang wrote:
> Remove redundant check for CPU feature S2FWB in dcache flush code
> to save some CPU cycles for every memslot flush and unmapping.
> And move the S2FWB check to outer functions to avoid future
> redundancy and keep consistent with other
On Mon, Jan 25, 2021 at 10:10:43PM +0800, Yanan Wang wrote:
> With a guest translation fault, we don't really need the memcache pages
> when only installing a new entry to the existing page table or replacing
> the table entry with a block entry. And with a guest permission fault,
> we also don't
On Mon, Jan 25, 2021 at 10:10:44PM +0800, Yanan Wang wrote:
> After dirty-logging is stopped for a VM configured with huge mappings,
> KVM will recover the table mappings back to block mappings. As we only
> replace the existing page tables with a block entry and the cacheability
> has not been
On Mon, Mar 08, 2021 at 01:30:53PM +, Will Deacon wrote:
> On Sun, Mar 07, 2021 at 05:24:21PM +0530, Anshuman Khandual wrote:
> > On 3/5/21 8:21 PM, Mark Rutland wrote:
> > > On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:
> > >> +#define
On Fri, 05 Mar 2021 14:36:09 +,
Anshuman Khandual wrote:
>
> From: James Morse
>
> As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
> might contain a range of values to describe supported translation granules
> (4K and 16K pages sizes in particular) instead of
On Fri, Mar 05, 2021 at 12:21:24PM -0800, Sami Tolvanen wrote:
> allmodconfig + CONFIG_LTO_CLANG_THIN=y fails to build due to following
> linker errors:
>
> ld.lld: error: irqbypass.c:(function __guest_enter: .text+0x21CC):
> relocation R_AARCH64_CONDBR19 out of range: 2031220 is not in
>
On Mon, Mar 08, 2021 at 01:38:07PM +, Quentin Perret wrote:
> On Monday 08 Mar 2021 at 12:46:07 (+), Will Deacon wrote:
> > > > > +static int host_stage2_idmap(u64 addr)
> > > > > +{
> > > > > + enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R |
> > > > > KVM_PGTABLE_PROT_W;
> > > > >
On Sun, Mar 07, 2021 at 05:24:21PM +0530, Anshuman Khandual wrote:
>
>
> On 3/5/21 8:21 PM, Mark Rutland wrote:
> > On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:
> >> From: James Morse
> >>
> >> As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
>
On Friday 05 Mar 2021 at 19:29:06 (+), Will Deacon wrote:
> On Tue, Mar 02, 2021 at 02:59:59PM +, Quentin Perret wrote:
> > +static __always_inline void __load_host_stage2(void)
> > +{
> > + if (static_branch_likely(_protected_mode_initialized))
> > +
On Mon, Mar 08, 2021 at 09:22:29AM +, Quentin Perret wrote:
> On Friday 05 Mar 2021 at 19:29:06 (+), Will Deacon wrote:
> > On Tue, Mar 02, 2021 at 02:59:59PM +, Quentin Perret wrote:
> > > +static __always_inline void __load_host_stage2(void)
> > > +{
> > > + if
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