Hey Marc,
On Monday 22 Mar 2021 at 16:48:27 (+), Marc Zyngier wrote:
> In protected mode, late CPUs are not allowed to boot (enforced by
> the PSCI relay). We can thus specialise the read_ctr macro to
> always return a pre-computed, sanitised value.
>
> Signed-off-by: Marc Zyngier
> ---
> a
On Mon, 22 Mar 2021 17:40:40 +,
Quentin Perret wrote:
>
> Hey Marc,
>
> On Monday 22 Mar 2021 at 16:48:27 (+), Marc Zyngier wrote:
> > In protected mode, late CPUs are not allowed to boot (enforced by
> > the PSCI relay). We can thus specialise the read_ctr macro to
> > always return a p
On Fri, Mar 12, 2021 at 06:32:02PM +0100, Eric Auger wrote:
> The tests exercise the VGIC_V3 device creation including the
> associated KVM_DEV_ARM_VGIC_GRP_ADDR group attributes:
>
> - KVM_VGIC_V3_ADDR_TYPE_DIST/REDIST
> - KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION
>
> Some other tests dedicate to KVM_
Hey Marc,
On Monday 22 Mar 2021 at 13:44:38 (+), Marc Zyngier wrote:
> I can't say I'm thrilled with this. Actually, it is fair to say that I
> don't like it at all! ;-)
:-)
> Copying whole structures with pointers that
> make no sense at EL2 feels... wrong.
And I don't disagree at all. I t
As we are about to specialise KVM's version of __flush_dcache_area
via a hack on the read_ctr macro, make sure that we won't ever
use KVM's copy of __flush_dcache_area(), as things would otherwise
break for late arriving CPUs.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/nvhe/cache.S | 4 +
[apologies for the noise: this is the real thing, please ignore the
previous posting... :-(]
Hi all,
Since Quentin's series is pretty close to final, I though that instead
of asking for additional rework, I'd have a go at it myself. These
patches try to bring some simplifications to the cpufeatur
In protected mode, late CPUs are not allowed to boot (enforced by
the PSCI relay). We can thus specialise the read_ctr macro to
always return a pre-computed, sanitised value.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/assembler.h | 9 +
arch/arm64/kernel/image-vars.h | 1
Now that the read_ctr macro has been specialised for nVHE,
the whole CPU_FTR_REG_HYP_COPY infrastrcture looks completely
overengineered.
Simplify it by populating the two u64 quantities (MMFR0 and 1)
that the hypervisor need.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h
In protected mode, late CPUs are not allowed to boot (enforced by
the PSCI relay). We can thus specialise the read_ctr macro to
always return a pre-computed, sanitised value.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/assembler.h | 9 +
arch/arm64/kernel/image-vars.h | 1
Now that the read_ctr macro has been specialised for nVHE,
the whole CPU_FTR_REG_HYP_COPY infrastrcture looks completely
overengineered.
Simplify it by populating the two u64 quantities (MMFR0 and 1)
that the hypervisor need.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h
Hi all,
Since Quentin's series is pretty close to final, I though that instead
of asking for additional rework, I'd have a go at it myself. These
patches try to bring some simplifications to the cpufeature
duplication that has been introduced between EL1 and EL2.
This whole infrastructure exists
As we are about to specialise KVM's version of __flush_dcache_area
via a hack opn the read_ctr macro, make sure that we won't ever
use KVM's copy of __flush_dcache_area(), as things would otherwise
break for late arriving CPUs.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/nvhe/cache.S | 4
Some fields in SCTLR_EL1 are UNKNOWN at reset and the arm64 boot
requirements, as stated by Linux in Documentation/arm64/booting.rst, do not
specify a particular value for all the fields. Do not rely on the good will
of the hypervisor and userspace to set SCTLR_EL1 to a sane value (by their
definit
Compute the dcache line size when doing dcache maintenance instead of using
a global variable computed in setup(), which allows us to do dcache
maintenance at any point in the boot process. This will be useful for
running as an EFI app and it also aligns our implementation to that of the
Linux kern
Move system register field definitions to sysreg.h, where the opcodes for
system register access are defined, to align ourselves with the Linux
kernel. EL2 support, needed for EFI and nested virtualization testing, will
require additional register and field definions, and having them in the
same pl
The dcache_by_line_op macro executes a DSB to complete the cache
maintenance operations. According to ARM DDI 0487G.a, page B2-150:
"In addition, no instruction that appears in program order after the DSB
instruction can alter any state of the system or perform any part of its
functionality until
>From an architectural point of view, the PE can speculate instruction
fetches and data reads at any time when the MMU is enabled using the
translation tables from TTBR0_EL1 and TTBR1_EL1. kvm-unit-tests uses an
identity map, and as such it only programs TTBR0_EL1 with a valid table and
leaves TTBR
This series is mostly fixes and cleanups for things I found when playing
with EFI support. Most of them I hope are fairly self-explanatory.
What is clearly aimed at running on baremetal is patch #2 ("arm/arm64:
Remove dcache_line_size global variable"), which is needed because the
startup environm
Software can use the SPSel operand to write directly to PSTATE.SP.
According to ARM DDI 0487F.b, page D1-2332, writes to PSTATE are
self-synchronizing and no ISB is needed:
"Writes to the PSTATE fields have side-effects on various aspects of the PE
operation. All of these side-effects are guarante
Hi Quentin,
On Fri, 19 Mar 2021 10:01:21 +,
Quentin Perret wrote:
>
> Introduce the infrastructure in KVM enabling to copy CPU feature
> registers into EL2-owned data-structures, to allow reading sanitised
> values directly at EL2 in nVHE.
>
> Given that only a subset of these features are
Hi Alex,
On 2021/3/19 23:07, Alexandru Elisei wrote:
Hi Yanan,
Sorry for taking so long to reply, been busy with other things unfortunately.
Still appreciate your patient reply! :)
I
did notice that you sent a new version of this series, but I would like to
continue our discussion on this pat
On Fri, Mar 19, 2021 at 10:01:40AM +, Quentin Perret wrote:
> In order to further configure stage 2 page-tables, pass flags to the
> init function using a new enum.
>
> The first of these flags allows to disable FWB even if the hardware
> supports it as we will need to do so for the host stage
Hi Andre,
On 3/16/21 3:40 PM, Andre Przywara wrote:
> On Mon, 15 Mar 2021 15:46:09 +
> Alexandru Elisei wrote:
>
> Hi Alex,
>
>> On 3/4/21 3:00 PM, Andre Przywara wrote:
>>> On Sat, 27 Feb 2021 10:41:57 +
>>> Alexandru Elisei wrote:
>>>
Compute the dcache line size when doing dcac
On Fri, Mar 19, 2021 at 10:01:41AM +, Quentin Perret wrote:
> Introduce a new stage 2 configuration flag to specify that all mappings
> in a given page-table will be identity-mapped, as will be the case for
> the host. This allows to introduce sanity checks in the map path and to
> avoid progra
On Fri, Mar 19, 2021 at 10:01:37AM +, Quentin Perret wrote:
> As the host stage 2 will be identity mapped, all the .hyp memory regions
> and/or memory pages donated to protected guestis will have to marked
> invalid in the host stage 2 page-table. At the same time, the hypervisor
> will need a
On Fri, Mar 19, 2021 at 10:01:22AM +, Quentin Perret wrote:
> We will need to do cache maintenance at EL2 soon, so compile a copy of
> __flush_dcache_area at EL2, and provide a copy of arm64_ftr_reg_ctrel0
> as it is needed by the read_ctr macro.
>
> Signed-off-by: Quentin Perret
> ---
> arc
On Fri, Mar 19, 2021 at 10:01:21AM +, Quentin Perret wrote:
> Introduce the infrastructure in KVM enabling to copy CPU feature
> registers into EL2-owned data-structures, to allow reading sanitised
> values directly at EL2 in nVHE.
>
> Given that only a subset of these features are being read
Hi Eric,
在 2021/3/20 1:36, Auger Eric 写道:
Hi Chenxiang,
On 3/4/21 8:55 AM, chenxiang (M) wrote:
Hi Eric,
在 2021/2/24 4:56, Eric Auger 写道:
Implement domain-selective, pasid selective and page-selective
IOTLB invalidations.
Signed-off-by: Eric Auger
---
v13 -> v14:
- Add domain invalidat
On Fri, Mar 19, 2021 at 04:53:59PM +, Alexandru Elisei wrote:
> Currently, the UART early address is set indirectly with the --vmm option
> and there are only two possible values: if the VMM is qemu (the default),
> then the UART address is set to 0x0900; if the VMM is kvmtool, then the
> U
Hi Chenxiang,
On 3/22/21 7:40 AM, chenxiang (M) wrote:
> Hi Eric,
>
>
> 在 2021/3/20 1:36, Auger Eric 写道:
>> Hi Chenxiang,
>>
>> On 3/4/21 8:55 AM, chenxiang (M) wrote:
>>> Hi Eric,
>>>
>>>
>>> 在 2021/2/24 4:56, Eric Auger 写道:
Implement domain-selective, pasid selective and page-selective
>>
30 matches
Mail list logo
