On 2022-02-01 16:51, Russell King (Oracle) wrote:
On Fri, Jan 28, 2022 at 12:18:23PM +, Marc Zyngier wrote:
HCR_EL2.E2H is nasty, as a flip of this bit completely changes the way
we deal with a lot of the state. So when the guest flips this bit
(sysregs are live), do the put/load dance so
On Fri, Jan 28, 2022 at 12:18:27PM +, Marc Zyngier wrote:
> From: Jintack Lim
>
> For the same reason we trap virtual memory register accesses at virtual
> EL2, we need to trap SPSR_EL1, ELR_EL1 and VBAR_EL1 accesses. ARM v8.3
> introduces the HCR_EL2.NV1 bit to be able to trap on those
On Fri, Jan 28, 2022 at 12:18:26PM +, Marc Zyngier wrote:
> From: Christoffer Dall
>
> When running in virtual EL2 mode, we actually run the hardware in EL1
> and therefore have to use the EL1 registers to ensure correct operation.
>
> By setting the HCR.TVM and HCR.TVRM we ensure that the
On Fri, Jan 28, 2022 at 12:18:25PM +, Marc Zyngier wrote:
> From: Christoffer Dall
>
> We can no longer blindly copy the VCPU's PSTATE into SPSR_EL2 and return
> to the guest and vice versa when taking an exception to the hypervisor,
> because we emulate virtual EL2 in EL1 and therefore have
On Fri, Jan 28, 2022 at 12:18:23PM +, Marc Zyngier wrote:
> HCR_EL2.E2H is nasty, as a flip of this bit completely changes the way
> we deal with a lot of the state. So when the guest flips this bit
> (sysregs are live), do the put/load dance so that we have a consistent
> state.
>
> Yes,
On Fri, Jan 28, 2022 at 12:18:22PM +, Marc Zyngier wrote:
> SPSR_EL2 needs special attention when running nested on ARMv8.3:
>
> If taking an exception while running at vEL2 (actually EL1), the
> HW will update the SPSR_EL1 register with the EL1 mode. We need
> to track this in order to make
On Fri, Jan 28, 2022 at 12:18:21PM +, Marc Zyngier wrote:
> KVM internally uses accessor functions when reading or writing the
> guest's system registers. This takes care of accessing either the stored
> copy or using the "live" EL1 system registers when the host uses VHE.
>
> With the
On Fri, Jan 28, 2022 at 12:18:20PM +, Marc Zyngier wrote:
> Some EL2 system registers immediately affect the current execution
> of the system, so we need to use their respective EL1 counterparts.
> For this we need to define a mapping between the two. In general,
> this only affects non-VHE
On Tue, Feb 01, 2022 at 01:10:13PM +, Alex Bennée wrote:
>
> Gentle ping, I'm trying to clear this off my internal JIRA so let me
> know if you want me to do anything to help.
>
Sorry Alex! I've been juggling too many balls lately and completely
dropped this one. I'll rebase arm/queue now
On Fri, Jan 28, 2022 at 12:18:15PM +, Marc Zyngier wrote:
> From: Jintack Lim
>
> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
> this bit is set, accessing EL2 registers in EL1 traps to EL2. In
> addition, executing the following instructions in EL1 will trap to
On Fri, Jan 28, 2022 at 12:18:09PM +, Marc Zyngier wrote:
> From: Jintack Lim
>
> Add a new ARM64_HAS_NESTED_VIRT feature to indicate that the
> CPU has the ARMv8.3 nested virtualization capability, together
> with the 'kvm-arm.mode=nested' command line option.
>
> This will be used to
Andrew Jones writes:
> On Tue, Nov 30, 2021 at 02:11:34PM +, Alex Bennée wrote:
>>
>> Andrew Jones writes:
>>
>> > On Fri, Nov 19, 2021 at 04:30:47PM +, Alex Bennée wrote:
>> >>
>> >> Andrew Jones writes:
>> >>
>> >> > On Fri, Nov 12, 2021 at 02:08:01PM +, Alex Bennée wrote:
On 1/31/22 5:04 PM, Ard Biesheuvel wrote:
On Mon, 31 Jan 2022 at 17:03, Marc Zyngier wrote:
It appears that the way INTx is emulated is "slightly" out of spec
in kvmtool. We happily inject an edge interrupt, even if the spec
mandates a level.
This doesn't change much for either the guest
On 1/31/22 5:04 PM, Ard Biesheuvel wrote:
On Mon, 31 Jan 2022 at 17:03, Marc Zyngier wrote:
It appears that the way INTx is emulated is "slightly" out of spec
in kvmtool. We happily inject an edge interrupt, even if the spec
mandates a level.
This doesn't change much for either the guest
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