Hi Marc,
On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
>
> Allow userspace to write ID_DFR0_EL1, on the condition that only
> the PerfMon field can be altered and be something that is compatible
> with what was computed for the AArch64 view of the guest.
>
> Signed-off-by: Marc Zyngier
> -
On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
>
> Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
> the PMUver field can be altered and be at most the one that was
> initially computed for the guest.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Reiji Watanabe
Use the dedicated non-atomic helpers for {clear,set}_bit() and their
test variants, i.e. the double-underscore versions. Depsite being
defined in atomic.h, and despite the kernel versions being atomic in the
kernel, tools' {clear,set}_bit() helpers aren't actually atomic. Move
to the double-under
Convert {clear,set}_bit() to atomics as KVM's ucall implementation relies
on clear_bit() being atomic, they are defined in atomic.h, and the same
helpers in the kernel proper are atomic.
KVM's ucall infrastructure is the only user of clear_bit() in tools/, and
there are no true set_bit() users. t
Drop the "atomic_" prefix from tools' atomic_test_and_set_bit() to
match the kernel nomenclature where test_and_set_bit() is atomic,
and __test_and_set_bit() provides the non-atomic variant.
Signed-off-by: Sean Christopherson
---
tools/arch/x86/include/asm/atomic.h| 3 +--
tools/incl
Drop tools' non-atomic test_and_set_bit() and test_and_clear_bit() helpers
now that all users are gone. The names will be claimed in the future for
atomic versions.
Signed-off-by: Sean Christopherson
---
tools/include/linux/bitmap.h | 34 --
1 file changed, 34 de
Drop the vcpu param in the Hyper-V TLB flush test's call to
vm_get_page_table_entry(). Commit 751f280017b6 ("KVM: selftests: Drop
reserved bit checks from PTE accessor") eliminated the param, but the
in-flight patch to add the Hyper-V test didn't get the memo.
Fixes: a105ac64bef6 ("KVM: selftests
Take @bit as an unsigned long instead of a signed int in clear_bit() and
set_bit() so that they match the double-underscore versions, __clear_bit()
and __set_bit(). This will allow converting users that really don't want
atomic operations to the double-underscores without introducing a
functional
Use the dedicated non-atomic helpers for {clear,set}_bit() and their
test variants, i.e. the double-underscore versions. Depsite being
defined in atomic.h, and despite the kernel versions being atomic in the
kernel, tools' {clear,set}_bit() helpers aren't actually atomic. Move
to the double-under
Add a new ucall hook, GUEST_UCALL_NONE(), to allow tests to make ucalls
without allocating a ucall struct, and use it to enable single-step
in ARM's debug-exceptions test. Like the disable single-step path, the
enabling path also needs to ensure that no exclusive access sequences are
attempted aft
For obvious reasons I'd like to route the this through Paolo's tree.
In theory, taking just patch 5 through tip would work, but creating a
topic branch seems like the way to go, though maybe I'm being overly
paranoid. The current tip/perf/core doesn't have any conflicts, nor does
it have new set_b
Add rdmsr_from_l2() in hyperv_evmcs.c, it got left unintentionally omitted
when applying code review feeback on the fly. Intentionally duplicate
the code that's in hyperv_svm_test.c, the helper really should not exist
(L1 shouldn't clobber GPRs) and will hopefully be removed sooner than
later. Un
Signal that a test run is complete through perf_test_args instead of
having tests open code a similar solution. Ensure that the field resets
to false at the beginning of a test run as the structure is reused
between test runs, eliminating a couple of bugs:
access_tracking_perf_test hangs indefinit
Small series to add support for arm64 to access_tracking_perf_test and
correct a couple bugs along the way.
Tested on Ampere Altra w/ all supported guest modes.
v1 -> v2:
- Have perf_test_util indicate when to stop vCPU threads (Sean)
- Collect Gavin's R-b on the second patch. I left off Gavin'
Does exactly what it says on the tin.
Reviewed-by: Gavin Shan
Signed-off-by: Oliver Upton
---
tools/testing/selftests/kvm/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/testing/selftests/kvm/Makefile
b/tools/testing/selftests/kvm/Makefile
index 0172eb6cb6ee..4c0ff91a8964 10
Exclusive table walks are the only supported table walk in the hyp, as
there is no construct like RCU available in the hypervisor code. Reject
any attempt to do a shared table walk by returning an error and allowing
the caller to clean up the mess.
Suggested-by: Will Deacon
Signed-off-by: Oliver
Marek reported a BUG resulting from the recent parallel faults changes,
as the hyp stage-1 map walker attempted to allocate table memory while
holding the RCU read lock:
BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:274
in_atomic(): 0, irqs_disabled(): 0, non
Rather than passing through the state of the KVM_PGTABLE_WALK_SHARED
flag, just take a pointer to the whole walker structure instead. Move
around struct kvm_pgtable and the RCU indirection such that the
associated ifdeffery remains in one place while ensuring the walker +
flags definitions precede
Small set of fixes for the parallel faults series. Most importantly,
stop taking the RCU read lock for walking hyp stage-1. For the sake of
consistency, take a pointer to kvm_pgtable_walker in
kvm_dereference_pteref() as well.
Tested on an Ampere Altra system with kvm-arm.mode={nvhe,protected} and
On Fri, Nov 18, 2022 at 12:19:50PM +, Will Deacon wrote:
> On Thu, Nov 17, 2022 at 06:23:23PM +, Oliver Upton wrote:
> > On Thu, Nov 17, 2022 at 05:49:52PM +, Will Deacon wrote:
> > > On Wed, Nov 16, 2022 at 04:56:55PM +, Oliver Upton wrote:
> >
> > [...]
> >
> > > > -static inlin
On Fri, Nov 18, 2022 at 02:56:38PM +, Will Deacon wrote:
> On Thu, Nov 10, 2022 at 01:53:26AM +, Oliver Upton wrote:
> > As the SMCCC (and related specifications) march towards an
> > 'everything and the kitchen sink' interface for interacting with a
> > system, it is less likely that KVM w
On Thu, Nov 17, 2022 at 08:43:17AM -0600, Rob Herring wrote:
> On Fri, Nov 4, 2022 at 10:55 AM Rob Herring wrote:
> >
> > This series adds support for Arm SPEv1.2 which is part of the
> > Armv8.7/Armv9.2 architecture. There's 2 new features that affect the
> > kernel: a new event filter bit, branc
On Fri, Nov 04, 2022 at 10:55:07AM -0500, Rob Herring wrote:
> Arm SPEv1.2 adds another 64-bits of event filtering control. As the
> existing perf_event_attr::configN fields are all used up for SPE PMU, an
> additional field is needed. Add a new 'config3' field.
>
> Tested-by: James Clark
> Signe
Hey Oliver,
On Thu, Nov 10, 2022 at 01:53:26AM +, Oliver Upton wrote:
> As the SMCCC (and related specifications) march towards an
> 'everything and the kitchen sink' interface for interacting with a
> system, it is less likely that KVM will implement every supported
> feature.
>
> Add a capa
On Thu, Nov 17, 2022 at 06:23:23PM +, Oliver Upton wrote:
> On Thu, Nov 17, 2022 at 05:49:52PM +, Will Deacon wrote:
> > On Wed, Nov 16, 2022 at 04:56:55PM +, Oliver Upton wrote:
>
> [...]
>
> > > -static inline void kvm_pgtable_walk_begin(void) {}
> > > -static inline void kvm_pgtabl
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