Hi Marc,
On Tue, Dec 20, 2022 at 08:09:21PM +, Marc Zyngier wrote:
> A recent development on the EFI front has resulted in guests having
> their page tables baked in the firmware binary, and mapped into
> the IPA space as part as a read-only memslot.
as part of a
> Not only this is legitimat
The former is an AArch32 legacy, so let's move over to the
verbose (and strictly identical) version.
This involves moving some of the #defines that were private
to KVM into the more generic esr.h.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/esr.h| 9 +
arch/arm64
As a minor optimisation, we can retrofit the "S1PTW is a write
even on translation fault" concept *if* the vcpu is using the
HW-managed Access Flag, as setting TCR_EL1.HA is guaranteed
to result in an update of the PTE.
However, we cannot do the same thing for DB, as it would require
us to parse t
Recent developments on the EFI front have resulted in guests that
simply won't boot if the page tables are in a read-only memslot and
that you're a bit unlucky in the way S2 gets paged in... The core
issue is related to the fact that we treat a S1PTW as a write, which
is close enough to what needs
A recent development on the EFI front has resulted in guests having
their page tables baked in the firmware binary, and mapped into
the IPA space as part as a read-only memslot.
Not only this is legitimate, but it also results in added security,
so thumbs up. However, this clashes mildly with our
On Thu, Dec 15, 2022 at 06:12:14PM +, Oliver Upton wrote:
> On Thu, Dec 15, 2022 at 09:33:17AM +, Ryan Roberts wrote:
> > On 15/12/2022 00:52, Oliver Upton wrote:
> > > On Tue, Dec 06, 2022 at 01:59:18PM +, Ryan Roberts wrote:
> > >> (appologies, I'm resending this series as I managed t
On Tue, Dec 20, 2022 at 09:01:19AM +, Ryan Roberts wrote:
> On 20/12/2022 00:06, Oliver Upton wrote:
> > Hi Ryan,
> >
> > On Tue, Dec 06, 2022 at 01:59:28PM +, Ryan Roberts wrote:
> >> In order to support 5 level translation, FEAT_LPA2 introduces the 1-bit
> >> SL2 field within VTCR_EL2 to
Alexandru Elisei writes:
Though I'm not sure how you managed to get MAX_SMP to go down to 6 cores
on
a 12 core machine. MAX_SMP is initialized to $(getconf _NPROCESSORS_ONLN),
so the body of the loop should never execute. I also tried it on a 6 core
machine, and MAX_SMP was 6, not 3.
Am I
Hi,
On Mon, Dec 19, 2022 at 06:52:50PM +, Colton Lewis wrote:
> This loop logic is broken for machines with a number of CPUs that
> isn't a power of two. A machine with 8 CPUs will test with MAX_SMP=8
> but a machine with 12 CPUs will test with MAX_SMP=6 because 12 >> 2 ==
> 6. This can, in ra
+ Mark
On Tue, 20 Dec 2022 10:50:24 +,
Dong Bo wrote:
>
> From: Nianyao Tang
>
> If we have VHE and need to reenable SME for host in
> kvm_arch_vcpu_put_fp, CPACR.SMEN is modified from 0 to 1. Trap
> control for reading SVCR is modified from enable to disable.
> Synchronization is needed b
On 20/12/2022 00:06, Oliver Upton wrote:
> Hi Ryan,
>
> On Tue, Dec 06, 2022 at 01:59:28PM +, Ryan Roberts wrote:
>> In order to support 5 level translation, FEAT_LPA2 introduces the 1-bit
>> SL2 field within VTCR_EL2 to extend the existing 2-bit SL0 field. The
>> SL2[0]:SL0[1:0] encodings hav
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