Before this change, the cache configuration of the physical CPU was
exposed to vcpus. This is problematic because the cache configuration a
vcpu sees varies when it migrates between vcpus with different cache
configurations.
Fabricate cache configuration from the sanitized value, which holds the
C
The CCSIDR access handler masks the associativity bits according to the
bit layout for processors without FEAT_CCIDX. KVM also assumes CCSIDR is
32-bit where it will be 64-bit if FEAT_CCIDX is enabled. Mask FEAT_CCIDX
so that these assumptions hold.
Suggested-by: Marc Zyngier
Signed-off-by: Akihi
Always set HCR_TID2 to trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and
CSSELR_EL1. This saves a few lines of code and allows to employ their
access trap handlers for more purposes anticipated by the old
condition for setting HCR_TID2.
Suggested-by: Marc Zyngier
Signed-off-by: Akihiko Odaki
---
arch/a
The macros are useful for KVM which needs to manage how CLIDR is exposed
to vcpu so move them to include/asm/cache.h, which KVM can refer to.
Signed-off-by: Akihiko Odaki
---
arch/arm64/include/asm/cache.h | 6 ++
arch/arm64/kernel/cacheinfo.c | 5 -
2 files changed, 6 insertions(+), 5
CCSIDR2_EL1 is available if FEAT_CCIDX is implemented as per
DDI0487I.a.
Signed-off-by: Akihiko Odaki
Reviewed-by: Mark Brown
---
arch/arm64/tools/sysreg | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 097d6faafc87..01d592cbc0ba 1
Convert CCSIDR_EL1 to automatic generation as per DDI0487I.a.
Signed-off-by: Akihiko Odaki
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 10 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/incl
From: Marc Zyngier
The CCSIDR_EL1 register contains an UNKNOWN field (which replaces
fields that were actually defined in previous revisions of the
architecture).
Define an 'Unkn' field type modeled after the Res0/Res1 types
to allow such description. This allows the generation of
#define CCS
Before this change, the cache configuration of the physical CPU was
exposed to vcpus. This is problematic because the cache configuration a
vcpu sees varies when it migrates between vcpus with different cache
configurations.
Fabricate cache configuration from the sanitized value, which holds the
C
On Wed, Dec 21, 2022 at 05:53:58PM +, Marc Zyngier wrote:
> On Wed, 21 Dec 2022 16:50:30 +,
> Oliver Upton wrote:
> >
> > On Wed, Dec 21, 2022 at 09:35:06AM +, Marc Zyngier wrote:
> >
> > [...]
> >
> > > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) {
> > > > > + /*
> > > > >
The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a
mask for fields in the ID registers. This macro has the assumption that
all feature fields are 4 bits wide but the architecture has evolved to
add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1,
so we nee
A while ago we introduced helpers which build on the generated defines for
the system registers which use token pasting to let us do FIELD_PREP() and
FIELD_GET() in a shorter and hopefully easier to read format, including one
specifically for enumerations. Update the bulk of the KVM code to use the
ions(-)
---
base-commit: e45fb347b630ee76482fe938ba76cf8eab811290
change-id: 20221221-kvm-sysreg-cleanup-dd618baabebb
Best regards,
--
Mark Brown
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On Wed, 21 Dec 2022 16:50:30 +,
Oliver Upton wrote:
>
> On Wed, Dec 21, 2022 at 09:35:06AM +, Marc Zyngier wrote:
>
> [...]
>
> > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) {
> > > > + /*
> > > > +* Only a permission fault on a S1PTW should be
> > > > +
On Wed, Dec 21, 2022 at 08:46:06AM -0800, Ricardo Koller wrote:
[...]
> > - return false;
> > + /* Can't introspect TCR_EL1 with pKVM */
> > + if (kvm_vm_is_protected(vcpu->kvm))
> > + return false;
> > +
> > +
Hi Ricardo,
On Wed, 21 Dec 2022 16:46:06 +,
Ricardo Koller wrote:
>
> Hello,
>
> On Tue, Dec 20, 2022 at 08:09:22PM +, Marc Zyngier wrote:
> > As a minor optimisation, we can retrofit the "S1PTW is a write
> > even on translation fault" concept *if* the vcpu is using the
> > HW-managed
On Wed, Dec 21, 2022 at 09:35:06AM +, Marc Zyngier wrote:
[...]
> > > + if (kvm_vcpu_abt_iss1tw(vcpu)) {
> > > + /*
> > > + * Only a permission fault on a S1PTW should be
> > > + * considered as a write. Otherwise, page tables baked
> > > + * in a read-only
Hello,
On Tue, Dec 20, 2022 at 08:09:22PM +, Marc Zyngier wrote:
> As a minor optimisation, we can retrofit the "S1PTW is a write
> even on translation fault" concept *if* the vcpu is using the
> HW-managed Access Flag, as setting TCR_EL1.HA is guaranteed
> to result in an update of the PTE.
>
On Tue, Dec 20, 2022 at 10:15:18AM +, Marc Zyngier wrote:
> Dong Bo wrote:
> > If we have VHE and need to reenable SME for host in
> > kvm_arch_vcpu_put_fp, CPACR.SMEN is modified from 0 to 1. Trap
> > control for reading SVCR is modified from enable to disable.
> > Synchronization is needed
On Tue, 20 Dec 2022 21:47:36 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Tue, Dec 20, 2022 at 08:09:21PM +, Marc Zyngier wrote:
> > A recent development on the EFI front has resulted in guests having
> > their page tables baked in the firmware binary, and mapped into
> > the IPA space as
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