Add a new test case to the vpmu_counter_access test to check
if PMU registers or their bits for unimplemented counters are not
accessible or are RAZ, as expected.
Signed-off-by: Reiji Watanabe
---
.../kvm/aarch64/vpmu_counter_access.c | 103 +-
.../selftests/kvm/include/a
Add a new test case to the vpmu_counter_access test to check if PMU
registers or their bits for implemented counters on the vCPU are
readable/writable as expected, and can be programmed to count events.
Signed-off-by: Reiji Watanabe
---
.../kvm/aarch64/vpmu_counter_access.c | 347 +++
Introduce vpmu_counter_access test for arm64 platforms.
The test configures PMUv3 for a vCPU, sets PMCR_EL1.N for the vCPU,
and check if the guest can consistently see the same number of the
PMU event counters (PMCR_EL1.N) that userspace sets.
This test case is done with each PMCR_EL1.N value that
Copy perf_event.h from the kernel's arch/arm64/include/asm/perf_event.h.
The following patches will use macros defined in this header.
Signed-off-by: Reiji Watanabe
---
tools/arch/arm64/include/asm/perf_event.h | 258 ++
1 file changed, 258 insertions(+)
create mode 100644 t
The number of PMU event counters is indicated in PMCR_EL0.N.
For a vCPU with PMUv3 configured, its value will be the same as
the host value by default. Userspace can set PMCR_EL0.N for the
vCPU to a lower value than the host value using KVM_SET_ONE_REG.
However, it is practically unsupported, as re
The default reset function for PMU registers (reset_pmu_reg())
now simply clears a specified register. Use that function for
PMUSERENR_EL0 and PMCCFILTR_EL0, since those registers should
simply be cleared on vCPU reset.
No functional change intended.
Signed-off-by: Reiji Watanabe
---
arch/arm64
On vCPU reset, PMCNTEN{SET,CLR}_EL1 and PMOVS{SET,CLR}_EL1 for
a vCPU are reset by reset_pmu_reg(). This function clears RAZ bits
of those registers corresponding to unimplemented event counters
on the vCPU, and sets bits corresponding to implemented event counters
to a predefined pseudo UNKNOWN va
The goal of this series is to allow userspace to limit the number
of PMU event counters on the vCPU.
The number of PMU event counters is indicated in PMCR_EL0.N.
For a vCPU with PMUv3 configured, its value will be the same as
the host value by default. Userspace can set PMCR_EL0.N for the
vCPU to
On 12/28/22 12:22, Marc Zyngier wrote:
Queued, thanks. I will leave this in kvm/queue after testing everything
else and moving it to kvm/next; this way, we can wait for test results
on other architectures.
Can you please make this a topic branch, and if possible based
on a released -rc? It w
On Wed, 24 Aug 2022 07:03:04 +0100,
Ganapatrao Kulkarni wrote:
>
> In NV case, Shadow stage 2 page table is created using host hypervisor
> page table configuration like page size, block size etc. Also, the shadow
> stage 2 table uses block level mapping if the Guest Hypervisor IPA is
> backed by
On Wed, 24 Aug 2022 07:03:03 +0100,
Ganapatrao Kulkarni wrote:
>
> Guest-Hypervisor forwards the timer interrupt to Guest-Guest, if it is
> enabled, unmasked and ISTATUS bit of register CNTV_CTL_EL0 is set for a
> loaded timer.
>
> For NV2 implementation, the Host-Hypervisor is not emulating the
On Wed, 24 Aug 2022 07:03:02 +0100,
Ganapatrao Kulkarni wrote:
>
> From: D Scott Phillips
>
> The timer emulation logic goes into an infinite loop when the NestedVM(L2)
> timer is being emulated.
>
> While the CPU is executing in L1 context, the L2 timers are emulated using
> host hrtimer. Whe
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