Hi Alex,
On 5/25/21 7:26 PM, Alex Bennée wrote:
> When running the test in TCG we are basically running on bare metal so
> don't rely on having a particular kernel errata applied.
>
> You might wonder why we handle this with a totally new test name
> instead of adjusting the append to take an ext
Hi Alex,
On 5/25/21 7:26 PM, Alex Bennée wrote:
> While an IRQ is not "guaranteed to be visible until an appropriate
> invalidation" it doesn't stop the actual implementation delivering it
> earlier if it wants to. This is the case for QEMU's TCG and as tests
> should only be checking architectura
Hi Alex,
On 5/25/21 7:26 PM, Alex Bennée wrote:
> With the support for TCG emulated GIC we can also test these now.
>
> Signed-off-by: Alex Bennée
> Cc: Shashi Mallela
Reviewed-by: Eric Auger
Eric
> ---
> arm/unittests.cfg | 2 --
> 1 file changed, 2 deletions(-)
igned-off-by: Alex Bennée
> Cc: Shashi Mallela
Reviewed-by: Eric Auger
Eric
> ---
> scripts/arch-run.bash | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/scripts/arch-run.bash b/scripts/arch-run.bash
> index 5997e38..70693f2 100644
> --- a/
Hi David, Marc,
On 5/4/21 4:47 PM, Auger Eric wrote:
> Hi David, Marc,
>
> On 8/5/20 7:56 PM, Marc Zyngier wrote:
>> From: David Brazdil
>>
>> Add new folders arch/arm64/kvm/hyp/{vhe,nvhe} and Makefiles for building code
>> that runs in EL2 under VHE/nVHE K
Hi Ricardo,
On 5/13/21 2:28 AM, Ricardo Koller wrote:
> Move GUEST_ASSERT_EQ to a common header, kvm_util.h, for other
> architectures and tests to use. Also modify __GUEST_ASSERT so it can be
> reused to implement GUEST_ASSERT_EQ.
>
> Signed-off-by: Ricardo Koller
Reviewed-by: Eric Auger
Than
Hi Ricardo,
On 5/13/21 2:27 AM, Ricardo Koller wrote:
> Hi,
>
> These patches add a debug exception test in aarch64 KVM selftests while
> also adding basic exception handling support.
>
> The structure of the exception handling is based on its x86 counterpart.
> Tests use the same calls to initi
Hi,
On 5/12/21 10:33 AM, Marc Zyngier wrote:
> On 2021-05-12 09:19, Auger Eric wrote:
>> Hi Ricardo,
>>
>> On 5/12/21 9:27 AM, Ricardo Koller wrote:
>>> On Fri, May 07, 2021 at 04:08:07PM +0200, Auger Eric wrote:
>>>> Hi Ricardo,
>>>>
>
Hi Ricardo,
On 5/12/21 9:27 AM, Ricardo Koller wrote:
> On Fri, May 07, 2021 at 04:08:07PM +0200, Auger Eric wrote:
>> Hi Ricardo,
>>
>> On 5/6/21 9:14 PM, Ricardo Koller wrote:
>>> On Thu, May 06, 2021 at 02:30:17PM +0200, Auger Eric wrote:
>>>> Hi Ri
Hi Marc,
On 5/5/21 8:03 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On Tue, 04 May 2021 15:47:36 +0100,
> Auger Eric wrote:
>>
>> Hi David, Marc,
>>
>> On 8/5/20 7:56 PM, Marc Zyngier wrote:
>>> From: David Brazdil
>>>
>>> Add new f
Hi Marc,
On 5/10/21 9:49 AM, Marc Zyngier wrote:
> Hi Eric,
>
> On Sun, 09 May 2021 18:00:04 +0100,
> Auger Eric wrote:
>>
>> Hi,
>> On 5/7/21 1:02 PM, Marc Zyngier wrote:
>>> On Fri, 07 May 2021 10:58:23 +0100,
>>> Shaokun Zhang wrote:
>>
Hi,
On 5/8/21 11:29 AM, Marc Zyngier wrote:
> On Sat, 08 May 2021 08:11:52 +0100,
> Zhu Lingshan wrote:
>>
>> This reverts commit a979a6aa009f3c99689432e0cdb5402a4463fb88.
>>
>> The reverted commit may cause VM freeze on arm64 platform.
>> Because on arm64 platform, stop a consumer will suspend th
Hi,
On 5/7/21 1:02 PM, Marc Zyngier wrote:
> On Fri, 07 May 2021 10:58:23 +0100,
> Shaokun Zhang wrote:
>>
>> Hi Marc,
>>
>> Thanks for your quick reply.
>>
>> On 2021/5/7 17:03, Marc Zyngier wrote:
>>> On Fri, 07 May 2021 06:57:04 +0100,
>>> Shaokun Zhang wrote:
[This letter comes from
Hi Ricardo,
On 5/6/21 9:14 PM, Ricardo Koller wrote:
> On Thu, May 06, 2021 at 02:30:17PM +0200, Auger Eric wrote:
>> Hi Ricardo,
>>
>
> Hi Eric,
>
> Thank you very much for the test.
>
>> On 5/3/21 9:12 PM, Ricardo Koller wrote:
>>> On Mon, May 03,
Hi Ricardo,
On 5/3/21 9:12 PM, Ricardo Koller wrote:
> On Mon, May 03, 2021 at 11:32:39AM +0100, Marc Zyngier wrote:
>> On Sat, 01 May 2021 00:24:06 +0100,
>> Ricardo Koller wrote:
>>>
>>> Add the infrastructure needed to enable exception handling in aarch64
>>> selftests. The exception handling
4 to report unhandled vectors as well.
>>
>> Tested: Forcing a page fault in the ./x86_64/xapic_ipi_test
>> halter_guest_code() shows this:
>>
>> $ ./x86_64/xapic_ipi_test
>> ...
>>Unexpected vectored event in guest (vector:0xe)
>>
>&
Hi Ricardo,
On 5/1/21 1:24 AM, Ricardo Koller wrote:
> Rename the vm_handle_exception function to a name that indicates more
> clearly that it installs something: vm_install_vector_handler.
>
> Suggested-by: Marc Zyngier
> Suggested-by: Andrew Jones
> Signed-off-by: Ricardo Koller
Reviewed-by:
Hi David, Marc,
On 8/5/20 7:56 PM, Marc Zyngier wrote:
> From: David Brazdil
>
> Add new folders arch/arm64/kvm/hyp/{vhe,nvhe} and Makefiles for building code
> that runs in EL2 under VHE/nVHE KVM, repsectivelly. Add an include folder for
> hyp-specific header files which will include code commo
Hi,
On 4/28/21 4:36 PM, Marc Zyngier wrote:
> On Wed, 28 Apr 2021 15:00:15 +0100,
> Alexandru Elisei wrote:
>>
>> I interpret that as that an INVALL guarantees that a change is
>> visible, but it the change can become visible even without the
>> INVALL.
>
> Yes. Expecting the LPI to be delivered
Hi Zenghui,
On 4/7/21 11:33 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2021/2/24 5:06, Eric Auger wrote:
>> +/*
>> + * VFIO_IOMMU_SET_PASID_TABLE - _IOWR(VFIO_TYPE, VFIO_BASE + 18,
>> + * struct vfio_iommu_type1_set_pasid_table)
>> + *
>> + * The SET operation passes a PASID table to the
Hi Zenghui,
On 4/7/21 9:39 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2021/2/24 4:56, Eric Auger wrote:
>> Up to now, when the type was UNMANAGED, we used to
>> allocate IOVA pages within a reserved IOVA MSI range.
>>
>> If both the host and the guest are exposed with SMMUs, each
>> would allocate a
Hi Kunkun,
On 4/9/21 6:48 AM, Kunkun Jiang wrote:
> Hi Eric,
>
> On 2021/4/8 20:30, Auger Eric wrote:
>> Hi Kunkun,
>>
>> On 4/1/21 2:37 PM, Kunkun Jiang wrote:
>>> Hi Eric,
>>>
>>> On 2021/2/24 4:56, Eric Auger wrote:
>>>>
Hi Kunkun,
On 4/1/21 2:37 PM, Kunkun Jiang wrote:
> Hi Eric,
>
> On 2021/2/24 4:56, Eric Auger wrote:
>> With nested stage support, soon we will need to invalidate
>> S1 contexts and ranges tagged with an unmanaged asid, this
>> latter being managed by the guest. So let's introduce 2 helpers
>> t
Hi Drew,
On 4/6/21 5:09 PM, Andrew Jones wrote:
>
> Hi Eric,
>
> It looks like Marc already picked this patch up, but, FWIW, here's
> a few more comments you may consider.
I will send a fixup patch on top of the one taken my Marc. Few comments
below.
>
> On Mon, Apr 05, 2021 at 06:39:41PM +02
Hi Marc,
On 4/5/21 12:12 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On Sun, 04 Apr 2021 18:22:35 +0100,
> Eric Auger wrote:
>>
>> While writting vgic v3 init sequence KVM selftests I noticed some
>> relatively minor issues. This was also the opportunity to try to
>> fix the issue laterly reported by
Hi Marc,
On 4/5/21 12:10 PM, Marc Zyngier wrote:
> On Sun, 04 Apr 2021 18:22:42 +0100,
> Eric Auger wrote:
>>
>> Commit 23bde34771f1 ("KVM: arm64: vgic-v3: Drop the
>> reporting of GICR_TYPER.Last for userspace") temporarily fixed
>> a bug identified when attempting to access the GICR_TYPER
>> re
Hi Marc,
On 4/1/21 7:30 PM, Marc Zyngier wrote:
> On Thu, 01 Apr 2021 18:03:25 +0100,
> Auger Eric wrote:
>>
>> Hi Marc,
>>
>> On 4/1/21 3:42 PM, Marc Zyngier wrote:
>>> Hi Eric,
>>>
>>> On Thu, 01 Apr 2021 09:52:37 +0100,
>>> E
Hi Marc,
On 4/1/21 3:42 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On Thu, 01 Apr 2021 09:52:37 +0100,
> Eric Auger wrote:
>>
>> Commit 23bde34771f1 ("KVM: arm64: vgic-v3: Drop the
>> reporting of GICR_TYPER.Last for userspace") temporarily fixed
>> a bug identified when attempting to access the GIC
Hi Shameer,
On 4/1/21 2:38 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 01 April 2021 12:49
>> To: yuzenghui
>> Cc: eric.auger@gmail.com; io...@lists.linux-foundation.
Hi Zenghui,
On 4/1/21 8:11 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2021/2/24 4:56, Eric Auger wrote:
>> +static int
>> +arm_smmu_cache_invalidate(struct iommu_domain *domain, struct device
>> *dev,
>> + struct iommu_cache_invalidate_info *inv_info)
>> +{
>> + struct arm_smmu_cmdq_
Hi Zenghui,
On 3/30/21 11:23 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2021/2/24 4:56, Eric Auger wrote:
>> In preparation for vSVA, let's accept userspace provided configs
>> with more than one CD. We check the max CD against the host iommu
>> capability and also the format (linear versus 2 level)
Hi Marc,
On 4/1/21 12:52 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On Thu, 01 Apr 2021 09:52:31 +0100,
> Eric Auger wrote:
>>
>> KVM_DEV_ARM_VGIC_GRP_ADDR group doc says we should return
>> -EEXIST in case the base address of the redist is already set.
>> We currently return -EINVAL.
>>
>> However
Hi Zenghui,
On 3/30/21 11:17 AM, Zenghui Yu wrote:
> On 2021/2/24 4:56, Eric Auger wrote:
>> @@ -1936,7 +1950,12 @@ static void
>> arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size,
>> },
>> };
>> - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
>> + if (ext_as
Hi Drew,
On 3/22/21 7:32 PM, Andrew Jones wrote:
> On Fri, Mar 12, 2021 at 06:32:02PM +0100, Eric Auger wrote:
>> The tests exercise the VGIC_V3 device creation including the
>> associated KVM_DEV_ARM_VGIC_GRP_ADDR group attributes:
>>
>> - KVM_VGIC_V3_ADDR_TYPE_DIST/REDIST
>> - KVM_VGIC_V3_ADDR_T
Hi Chenxiang,
On 3/22/21 7:40 AM, chenxiang (M) wrote:
> Hi Eric,
>
>
> 在 2021/3/20 1:36, Auger Eric 写道:
>> Hi Chenxiang,
>>
>> On 3/4/21 8:55 AM, chenxiang (M) wrote:
>>> Hi Eric,
>>>
>>>
>>> 在 2021/2/24 4:56, Eric Auger 写道:
&
Hi Chenxiang,
On 3/4/21 8:55 AM, chenxiang (M) wrote:
> Hi Eric,
>
>
> 在 2021/2/24 4:56, Eric Auger 写道:
>> Implement domain-selective, pasid selective and page-selective
>> IOTLB invalidations.
>>
>> Signed-off-by: Eric Auger
>>
>> ---
>>
>> v13 -> v14:
>> - Add domain invalidation
>> - do glob
Hi Krishna,
On 3/18/21 1:16 AM, Krishna Reddy wrote:
> Tested-by: Krishna Reddy
>
> Validated nested translations with NVMe PCI device assigned to Guest VM.
> Tested with both v12 and v13 of Jean-Philippe's patches as base.
Many thanks for that.
>
>> This is based on Jean-Philippe's
>> [PATCH
Hi Keqian,
On 3/2/21 9:35 AM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2021/2/24 4:56, Eric Auger wrote:
>> On attach_pasid_table() we program STE S1 related info set
>> by the guest into the actual physical STEs. At minimum
>> we need to program the context descriptor GPA and compute
>> whether the s
Hi Krishna,
On 3/15/21 7:04 PM, Krishna Reddy wrote:
> Tested-by: Krishna Reddy
>
>> 1) pass the guest stage 1 configuration
>
> Validated Nested SMMUv3 translations for NVMe PCIe device from Guest VM along
> with patch series "v11 SMMUv3 Nested Stage Setup (VFIO part)" and QEMU patch
> series
Hi Alexandru,
On 2/19/21 1:13 PM, Alexandru Elisei wrote:
> The LPI code validates a result similarly to the IPI tests, by checking if
> the target CPU received the interrupt with the expected interrupt number.
> However, the LPI tests invent their own way of checking the test results by
> creatin
Hi Alexandru,
On 1/20/21 4:56 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 1/14/21 10:02 AM, Auger Eric wrote:
>> Hi Alexandru,
>>
>> On 1/12/21 3:55 PM, Alexandru Elisei wrote:
>>> Hi Eric,
>>>
>>> On 12/12/20 6:50 PM, Eric Auger wrote
Hi Alexandru,
On 1/20/21 5:13 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 1/14/21 10:16 AM, Auger Eric wrote:
>> Hi Alexandru,
>>
>> On 1/12/21 6:02 PM, Alexandru Elisei wrote:
>>> Hi Eric,
>>>
>>> On 12/12/20 6:50 PM, Eric Auger wrote:
&g
Hi Marc,
On 3/11/21 11:00 AM, Marc Zyngier wrote:
> KVM/arm64 has forever used a 40bit default IPA space, partially
> due to its 32bit heritage (where the only choice is 40bit).
>
> However, there are implementations in the wild that have a *cough*
> much smaller *cough* IPA space, which leads to
Hi Marc,
On 3/10/21 11:42 AM, Marc Zyngier wrote:
> KVM/arm64 has forever used a 40bit default IPA space, partially
> due to its 32bit heritage (where the only choice is 40bit).
>
> However, there are implementations in the wild that have a *cough*
> much smaller *cough* IPA space, which leads to
Hi Marc,
On 3/10/21 11:42 AM, Marc Zyngier wrote:
> When registering a memslot, we check the size and location of that
> memslot against the IPA size to ensure that we can provide guest
> access to the whole of the memory.
>
> Unfortunately, this check rejects memslot that end-up at the exact
> l
Hi Jean,
On 3/5/21 11:45 AM, Jean-Philippe Brucker wrote:
> Hi,
>
> On Tue, Feb 23, 2021 at 10:06:15PM +0100, Eric Auger wrote:
>> This patch adds the VFIO_IOMMU_SET_MSI_BINDING ioctl which aim
>> to (un)register the guest MSI binding to the host. This latter
>> then can use those stage 1 binding
Hi Shameer, all
On 2/23/21 9:56 PM, Eric Auger wrote:
> This series brings the IOMMU part of HW nested paging support
> in the SMMUv3. The VFIO part is submitted separately.
>
> This is based on Jean-Philippe's
> [PATCH v12 00/10] iommu: I/O page faults for SMMUv3
> https://lore.kernel.org/linux-
Hi Shenming,
On 2/23/21 1:45 PM, Shenming Lu wrote:
>> +static int vfio_pci_dma_fault_init(struct vfio_pci_device *vdev)
>> +{
>> +struct vfio_region_dma_fault *header;
>> +struct iommu_domain *domain;
>> +size_t size;
>> +bool nested;
>> +int ret;
>> +
>> +domain = iommu_g
Hi Keqian,
On 2/22/21 1:20 PM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2021/2/22 18:53, Auger Eric wrote:
>> Hi Keqian,
>>
>> On 2/2/21 1:34 PM, Keqian Zhu wrote:
>>> Hi Eric,
>>>
>>> On 2020/11/16 19:00, Eric Auger wrote
Hi Keqian,
On 2/2/21 1:34 PM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2020/11/16 19:00, Eric Auger wrote:
>> From: "Liu, Yi L"
>>
>> This patch adds an VFIO_IOMMU_SET_PASID_TABLE ioctl
>> which aims to pass the virtual iommu guest configuration
>> to the host. This latter takes the form of the so-ca
Hi Shameer,
On 1/8/21 6:05 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: 18 November 2020 11:22
>> To: eric.auger@gmail.com; eric.au...@redhat.com;
>> io...@lists.linux-foundation.org; linux-ker...@vg
Hi Shameer,
On 2/18/21 11:36 AM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>>> -Original Message-
>>> From: Eric Auger [mailto:eric.au...@redhat.com]
>>> Sent: 16 November 2020 11:00
>>> To: eric.auger@gmail.com; eric.au...@redhat.com;
>>> io...@lists.linux-foundation.org; linux-k
Hi Keqian,
On 2/18/21 9:43 AM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2021/2/12 16:55, Auger Eric wrote:
>> Hi Keqian,
>>
>> On 2/1/21 12:52 PM, Keqian Zhu wrote:
>>> Hi Eric,
>>>
>>> On 2020/11/18 19:21, Eric Auger wrote:
>>>> On
Hi Shameer,
On 12/3/20 7:42 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: kvmarm-boun...@lists.cs.columbia.edu
>> [mailto:kvmarm-boun...@lists.cs.columbia.edu] On Behalf Of Auger Eric
>> Sent: 01 December 2020 13:59
>>
Hi Keqian,
On 2/1/21 12:52 PM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2020/11/18 19:21, Eric Auger wrote:
>> On ARM, MSI are translated by the SMMU. An IOVA is allocated
>> for each MSI doorbell. If both the host and the guest are exposed
>> with SMMUs, we end up with 2 different IOVAs allocated by
Hi Keqian,
On 2/2/21 8:14 AM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2020/11/18 19:21, Eric Auger wrote:
>> When nested stage translation is setup, both s1_cfg and
>> s2_cfg are set.
>>
>> We introduce a new smmu domain abort field that will be set
>> upon guest stage1 configuration passing.
>>
>> a
Hi Keqian,
On 2/2/21 9:03 AM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2020/11/18 19:21, Eric Auger wrote:
>> On attach_pasid_table() we program STE S1 related info set
>> by the guest into the actual physical STEs. At minimum
>> we need to program the context descriptor GPA and compute
>> whether the
Hi Alexandru,
On 1/29/21 5:36 PM, Alexandru Elisei wrote:
> The LPI code validates a result similarly to the IPI tests, by checking if
> the target CPU received the interrupt with the expected interrupt number.
> However, the LPI tests invent their own way of checking the test results by
> creatin
Hi Alexandru,
On 1/29/21 5:36 PM, Alexandru Elisei wrote:
> check_acked() has several peculiarities: is the only function among the
> check_* functions which calls report() directly, it does two things
> (waits for interrupts and checks for misfired interrupts) and it also
> mixes printf, report_i
has fired after the invalidation.
> Leave the check after the INT command to make sure the INT command still
> works for the now re-enabled LPI.
>
> CC: Auger Eric
> Suggested-by: Zenghui Yu
> Reviewed-by: Andre Przywara
> Signed-off-by: Alexandru Elisei
Reviewed-by: Er
Hi Alexandru,
On 1/29/21 5:36 PM, Alexandru Elisei wrote:
> GICv2 generates IPIs with a MMIO write to the GICD_SGIR register. A common
> pattern for IPI usage is for the IPI receiver to read data written to
> memory by the sender. The armv7 and armv8 architectures implement a
> weakly-ordered memo
.litmus from
> tools/memory-model/litmus-tests. More examples and explanations can be
> found in the Linux source tree, in Documentation/memory-barriers.txt, in
> the sections "SMP BARRIER PAIRING" and "READ MEMORY BARRIERS VS LOAD
> SPECULATION".
>
> For con
same barrier is executed by readl() after the MMIO read.
> Together with the wmb() barrier from writel() when triggering the IPI,
> this ensures that the expected memory ordering is respected.
>
> Signed-off-by: Alexandru Elisei
Reviewed-by: Eric Auger
Eric
> ---
> arm/
Hi,
On 2/3/21 12:20 PM, Marc Zyngier wrote:
> On 2021-02-03 11:07, Auger Eric wrote:
>> Hi Marc,
>> On 2/3/21 11:36 AM, Marc Zyngier wrote:
>>> Hi Eric,
>>>
>>> On 2021-01-27 17:53, Auger Eric wrote:
>>>> Hi Marc,
>>>>
>>>
Hi Marc,
On 2/3/21 11:36 AM, Marc Zyngier wrote:
> Hi Eric,
>
> On 2021-01-27 17:53, Auger Eric wrote:
>> Hi Marc,
>>
>> On 1/25/21 1:26 PM, Marc Zyngier wrote:
>>> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
>>> pretty easy. All tha
Hi Keqian,
On 2/1/21 1:26 PM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2020/11/18 19:21, Eric Auger wrote:
>> From: Jean-Philippe Brucker
>>
>> When handling faults from the event or PRI queue, we need to find the
>> struct device associated to a SID. Add a rb_tree to keep track of SIDs.
>>
>> Signed
Hi Keqian,
On 2/1/21 12:27 PM, Keqian Zhu wrote:
> Hi Eric,
>
> On 2020/11/18 19:21, Eric Auger wrote:
>> In virtualization use case, when a guest is assigned
>> a PCI host device, protected by a virtual IOMMU on the guest,
>> the physical IOMMU must be programmed to be consistent with
>> the gue
Hi Marc,
On 1/25/21 1:26 PM, Marc Zyngier wrote:
> Instead of using a bunch of magic numbers, use the existing definitions
> that have been added since 8673e02e58410 ("arm64: perf: Add support
> for ARMv8.5-PMU 64-bit counters")
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/pmu-emul.c
Hi Marc,
On 1/25/21 1:26 PM, Marc Zyngier wrote:
> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
> pretty easy. All that is required is support for PMMIR_EL1, which
> is read-only, and for which returning 0 is a valid option as long
> as we don't advertise STALL_SLOT as an impleme
Hi Marc,
On 1/15/21 5:42 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On 2021-01-15 14:01, Auger Eric wrote:
>> Hi Marc,
>>
>> On 1/14/21 11:56 AM, Marc Zyngier wrote:
>>> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
>>> pretty easy.
Hi Marc,
On 1/14/21 11:56 AM, Marc Zyngier wrote:
> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
> pretty easy. All that is required is support for PMMIR_EL1, which
> is read-only, and for which returning 0 is a valid option.
>
> Let's just do that and adjust what we return to t
Hi Marc,
On 1/14/21 11:56 AM, Marc Zyngier wrote:
> Let's not pretend we support anything but ARMv8.0 as far as the
> debug architecture is concerned.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Eric Auger
Eric
> ---
> arch/arm64/kvm/sys_regs.c | 3 +++
> 1
n my previous comment here.
> - } else if (id == SYS_ID_DFR0_EL1) {
> + ID_AA64DFR0_PMUVER_SHIFT,
> + kvm_vcpu_has_pmu(vcpu) ?
> ID_AA64DFR0_PMUVER_8_1 : 0);
> + break;
>
ID_DFR0_PERFMON_8_1);
> + ID_DFR0_PERFMON_SHIFT,
> + kvm_vcpu_has_pmu(vcpu) ?
> ID_DFR0_PERFMON_8_1 : 0);
nit: Maybe you could use the same layout for SYS_ID_AA64DFR0_EL1
andremove cap there.
Hi Marc,
On 1/14/21 11:56 AM, Marc Zyngier wrote:
> The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current
> emulation doesn't set. Just add the missing bit.
>
> Reported-by: Peter Maydell
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/sys_regs.c | 2 +-
> 1 file changed, 1
Hi Marc,
On 1/14/21 11:56 AM, Marc Zyngier wrote:
> Despite advertising support for AArch32 PMUv3p1, we fail to handle
> the PMCEID{2,3} registers, which conveniently alias with with the top
s/with with/with
> bits of PMCEID{0,1}_EL1.
>
> Implement these registers with the usual AA32(HI/LO) alias
Hi Jean,
On 1/14/21 6:33 PM, Jean-Philippe Brucker wrote:
> Hi Eric,
>
> On Thu, Jan 14, 2021 at 05:58:27PM +0100, Auger Eric wrote:
>>>> The uacce-devel branches from
>>>>> https://github.com/Linaro/linux-kernel-uadk do provide this at the moment
>&g
Hi Shameer, Jean-Philippe,
On 12/4/20 11:23 AM, Auger Eric wrote:
> Hi Shameer, Jean-Philippe,
>
> On 12/4/20 11:20 AM, Shameerali Kolothum Thodi wrote:
>> Hi Jean,
>>
>>> -Original Message-
>>> From: Jean-Philippe Brucker [mailto:jean-phili...@li
Hi Alexandru,
On 1/12/21 6:02 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 12/12/20 6:50 PM, Eric Auger wrote:
>> Commit 23bde34771f1 ("KVM: arm64: vgic-v3: Drop the
>> reporting of GICR_TYPER.Last for userspace") temporarily fixed
>> a bug identified when attempting to access the GICR_TYPER
>>
Hi Alexandru,
On 1/6/21 5:32 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 12/12/20 6:50 PM, Eric Auger wrote:
>> KVM_DEV_ARM_VGIC_GRP_ADDR group doc says we should return
>> -EEXIST in case the base address of the redist is already set.
>> We currently return -EINVAL.
>>
>> However we need to re
Hi Alexandru,
On 1/12/21 3:55 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 12/12/20 6:50 PM, Eric Auger wrote:
>> has_run_once is set to true at the beginning of
>> kvm_vcpu_first_run_init(). This generally is not an issue
>> except when exercising the code with KVM selftests. Indeed,
>> if kvm_
Hi Marc,
On 12/28/20 4:35 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On Sat, 12 Dec 2020 18:50:04 +,
> Eric Auger wrote:
>>
>> vgic_register_all_redist_iodevs may succeed while
>> vgic_register_all_redist_iodevs fails. For example this can happen
>
> The same function cannot both fail and succe
Hi Marc,
On 12/28/20 4:41 PM, Marc Zyngier wrote:
> On Sat, 12 Dec 2020 18:50:05 +,
> Eric Auger wrote:
>>
>> On vgic_dist_destroy(), the addresses are not reset. However for
>> kvm selftest purpose this would allow to continue the test execution
>> even after a failure when running KVM_RUN.
Hi Alexandru,
On 1/6/21 6:12 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> The patch looks correct to me. kvm_vgic_addr() masks out all the bits except
> index
> from addr, so we don't need to do it in vgic_get_common_attr():
>
> Reviewed-by: Alexandru Elisei
>
> One nitpick below.
>
> On 12/12
Hi Alexandru,
On 1/12/21 5:16 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 1/12/21 4:04 PM, Alexandru Elisei wrote:
>> Hi Eric,
>>
>> On 12/12/20 6:50 PM, Eric Auger wrote:
>>> Instead of converting the vgic_io_device handle to a kvm_io_device
>>> handled and then do the oppositive, pass a vgic_i
Hi Alexandru,
On 1/12/21 4:39 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 12/12/20 6:50 PM, Eric Auger wrote:
>> kvm_arch_vcpu_precreate() returns -EBUSY if the vgic is
>> already initialized. So let's document that KVM_DEV_ARM_VGIC_CTRL_INIT
>> must be called after all vcpu creations.
>
> Che
Hi Shameer,
On 1/8/21 6:05 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: 18 November 2020 11:22
>> To: eric.auger@gmail.com; eric.au...@redhat.com;
>> io...@lists.linux-foundation.org; linux-ker...@v
Hi Alexandru,
On 12/16/20 12:40 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 12/15/20 1:58 PM, Auger Eric wrote:
>> Hi Alexandru,
>>
>> On 12/10/20 3:45 PM, Alexandru Elisei wrote:
>>> Hi Eric,
>>>
>>> On 12/3/20 1:39 PM, Auger Eric wrote:
Hi Shenming,
On 12/1/20 1:15 PM, Shenming Lu wrote:
> On 2020/12/1 19:50, Marc Zyngier wrote:
>> On 2020-12-01 11:40, Shenming Lu wrote:
>>> On 2020/12/1 18:55, Marc Zyngier wrote:
On 2020-11-30 07:23, Shenming Lu wrote:
Hi Shenming,
> We are pondering over this problem the
Hi Alexandru,
On 12/10/20 3:45 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> On 12/3/20 1:39 PM, Auger Eric wrote:
>>
>> On 11/25/20 4:51 PM, Alexandru Elisei wrote:
>>> check_acked() has several peculiarities: is the only function among the
>>> check_* func
Hi Alexandru,
On 12/14/20 3:02 PM, Alexandru Elisei wrote:
> Hi Eric,
>
> Thanks for having a look!
>
> On 12/14/20 1:48 PM, Auger Eric wrote:
>> Alexandru,
>>
>> On 12/1/20 4:01 PM, Alexandru Elisei wrote:
>>> KVM_ARM_VCPU_INIT ioctl calls kvm_rese
Alexandru,
On 12/1/20 4:01 PM, Alexandru Elisei wrote:
> KVM_ARM_VCPU_INIT ioctl calls kvm_reset_vcpu(), which in turn resets the
> PMU with a call to kvm_pmu_vcpu_reset(). The function zeroes the PMU
> chained counters bitmap and stops all the counters with a perf event
> attached. Because it is
Hi Alexandru,
On 12/1/20 4:01 PM, Alexandru Elisei wrote:
> vgic_v3_map_resources() returns -EBUSY if the VGIC isn't initialized,
> update the comment to kvm_vgic_map_resources() to match what the function
> does.
>
> Signed-off-by: Alexandru Elisei
> ---
> arch/arm64/kvm/vgic/vgic-init.c | 3 +
Hi Alexandru,
On 12/1/20 4:01 PM, Alexandru Elisei wrote:
> kvm_vgic_map_resources() is called when a VCPU if first run and it maps all
> the VGIC MMIO regions. To prevent double-initialization, the VGIC uses the
> ready variable to keep track of the state of resources and the global KVM
> mutex t
Hi Alexandru,
On 12/1/20 4:01 PM, Alexandru Elisei wrote:
> kvm_timer_enable() is called in kvm_vcpu_first_run_init() after
> kvm_vgic_map_resources() if the VGIC wasn't ready. kvm_vgic_map_resources()
> is the only place where kvm->arch.vgic.ready is set to true.
>
> For a v2 VGIC, kvm_vgic_map_
Hi Shameer, Jean-Philippe,
On 12/4/20 11:20 AM, Shameerali Kolothum Thodi wrote:
> Hi Jean,
>
>> -Original Message-
>> From: Jean-Philippe Brucker [mailto:jean-phili...@linaro.org]
>> Sent: 04 December 2020 09:54
>> To: Shameerali Kolothum Thodi
&
Hi Alexandru,
On 11/25/20 4:51 PM, Alexandru Elisei wrote:
> The LPI code validates a result similarly to the IPI tests, by checking if
> the target CPU received the interrupt with the expected interrupt number.
> However, the LPI tests invent their own way of checking the test results by
> creatin
Hi,
On 11/25/20 4:51 PM, Alexandru Elisei wrote:
> Testing that an interrupt is received as expected is done in three places:
> in check_ipi_sender(), check_irqnr() and check_acked(). check_irqnr()
> compares the interrupt ID with IPI_IRQ and records a failure in bad_irq,
> and check_ipi_sender()
On 11/25/20 4:51 PM, Alexandru Elisei wrote:
> check_acked() has several peculiarities: is the only function among the
> check_* functions which calls report() directly, it does two things
> (waits for interrupts and checks for misfired interrupts) and it also
> mixes printf, report_info and rep
Hi Alexandru,
On 11/25/20 4:51 PM, Alexandru Elisei wrote:
> The IPI test has two parts: in the first part, it tests that the sender CPU
> can send an IPI to itself (ipi_test_self()), and in the second part it
> sends interrupts to even-numbered CPUs (ipi_test_smp()). When acknowledging
> an inter
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