On Sun, Dec 01, 2019 at 12:20:18PM +, Marc Zyngier wrote:
> QEMU lacks the minimum Jazelle implementation that is required
> by the architecture (everything is RAZ or RAZ/WI). Add it
> together with the HCR_EL2.TID0 trapping that goes with it.
Looks good to me:
Reviewed-by: Edgar E.
he hierarchy.
>
> Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Marc Zyngier
> ---
> target/arm/helper.c | 31 +++
> 1 file changed, 27 insertions(+), 4 deletions(-)
>
> di
On Fri, Nov 29, 2019 at 09:24:37AM +, Marc Zyngier wrote:
> On 2019-11-29 08:28, Edgar E. Iglesias wrote:
> > On Thu, Nov 28, 2019 at 04:17:18PM +, Marc Zyngier wrote:
> > > HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> > > EL2, and that
PSCR:
> diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
> index 9710ef1c3e..44e538e51c 100644
> --- a/target/arm/vfp_helper.c
> +++ b/target/arm/vfp_helper.c
> @@ -1322,4 +1322,31 @@ float64 HELPER(frint64_d)(float64 f, void *fpst)
> return frint_d(f, fpst, 64);
&g
CPRegInfo *ri)
> return ret;
> }
>
> +static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo
> *ri,
> + bool isread)
> +{
> +if (arm_hcr_el2_eff(env) & HCR_TID1) {
> +return CP_ACCESS_TRA
On Thu, Nov 28, 2019 at 04:17:16PM +, Marc Zyngier wrote:
> HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
> CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
> completely ignores it, making impossible for hypervisors to
Nit: "making it impossible"
> virtual
f not running in a virtualized context.
>
> Fixes: 636540e9c40b
> Reported-by: Quentin Perret
> Signed-off-by: Marc Zyngier
Looks good to me:
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/helper.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
&g
