On 8/24/2020 11:35 AM, Florian Fainelli wrote:
Changes in v2:
- included missing preliminary patch to define the SB barrier instruction
Will Deacon (2):
arm64: Add support for SB barrier and patch in over DSB; ISB sequences
arm64: entry: Place an SB sequence following an ERET
Changes in v2:
- included missing preliminary patch to define the SB barrier instruction
Will Deacon (2):
arm64: Add support for SB barrier and patch in over DSB; ISB sequences
arm64: entry: Place an SB sequence following an ERET instruction
arch/arm64/include/asm/assembler.h | 13
]
Signed-off-by: Florian Fainelli
---
arch/arm64/kernel/entry.S | 2 ++
arch/arm64/kvm/hyp/entry.S | 2 ++
arch/arm64/kvm/hyp/hyp-entry.S | 4
3 files changed, 8 insertions(+)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index ca978d7d98eb..3408c782702c 100644
Changes in v2:
- included missing preliminary patch to define the SB barrier instruction
Will Deacon (2):
arm64: Add support for SB barrier and patch in over DSB; ISB sequences
arm64: entry: Place an SB sequence following an ERET instruction
arch/arm64/include/asm/assembler.h | 13
-by: Florian Fainelli
---
arch/arm64/kernel/entry.S | 2 ++
arch/arm64/kvm/hyp/entry.S | 2 ++
arch/arm64/kvm/hyp/hyp-entry.S | 4
3 files changed, 8 insertions(+)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index c1ffa95c0ad2..f70e0893ba51 100644
--- a/arch/arm64
ys_reg]
Signed-off-by: Florian Fainelli
---
arch/arm64/include/asm/assembler.h | 13 +
arch/arm64/include/asm/barrier.h| 4
arch/arm64/include/asm/cpucaps.h| 3 ++-
arch/arm64/include/asm/sysreg.h | 13 +
arch/arm64/include/asm/uaccess.h| 3 +--
arch
.
On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB
sequence and advertise the presence of the new instruction to userspace.
Signed-off-by: Will Deacon
[florian: adjust conflicts for cpucaps.h and cpufeature.c]
Signed-off-by: Florian Fainelli
---
arch/arm64/include/asm/assembler.h
at the point of an ERET, this could potentially be used as part of a
side-channel attack.
This patch emits an SB sequence after each ERET so that speculation is
held up on exception return.
Signed-off-by: Will Deacon
Signed-off-by: Florian Fainelli
---
arch/arm64/kernel/entry.S | 2 ++
arch
.
On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB
sequence and advertise the presence of the new instruction to userspace.
Signed-off-by: Will Deacon
[florian: adjust conflicts in cpucaps.h and cpufeature.c]
Signed-off-by: Florian Fainelli
---
arch/arm64/include/asm/assembler.h
On 8/24/2020 9:32 AM, Will Deacon wrote:
Hi Florian,
On Fri, Aug 21, 2020 at 10:16:23AM -0700, Florian Fainelli wrote:
On 8/21/20 9:03 AM, Will Deacon wrote:
On Fri, Aug 07, 2020 at 03:14:29PM +0200, Greg KH wrote:
On Thu, Aug 06, 2020 at 01:00:54PM -0700, Florian Fainelli wrote:
Greg
On 8/21/20 9:03 AM, Will Deacon wrote:
> On Fri, Aug 07, 2020 at 03:14:29PM +0200, Greg KH wrote:
>> On Thu, Aug 06, 2020 at 01:00:54PM -0700, Florian Fainelli wrote:
>>>
>>>
>>> On 7/20/2020 11:26 AM, Florian Fainelli wrote:
>>>> On 7/20/20 6:04 AM,
On 8/7/2020 11:17 AM, Florian Fainelli wrote:
On 8/7/2020 6:14 AM, Greg KH wrote:
On Thu, Aug 06, 2020 at 01:00:54PM -0700, Florian Fainelli wrote:
On 7/20/2020 11:26 AM, Florian Fainelli wrote:
On 7/20/20 6:04 AM, Greg KH wrote:
On Thu, Jul 09, 2020 at 12:50:23PM -0700, Florian
On 8/7/2020 6:14 AM, Greg KH wrote:
> On Thu, Aug 06, 2020 at 01:00:54PM -0700, Florian Fainelli wrote:
>>
>>
>> On 7/20/2020 11:26 AM, Florian Fainelli wrote:
>>> On 7/20/20 6:04 AM, Greg KH wrote:
>>>> On Thu, Jul 09, 2020 at 12:50:23PM -0700, Flori
On 7/20/2020 11:26 AM, Florian Fainelli wrote:
> On 7/20/20 6:04 AM, Greg KH wrote:
>> On Thu, Jul 09, 2020 at 12:50:23PM -0700, Florian Fainelli wrote:
>>> From: Will Deacon
>>>
>>> commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
>>
-by: Florian Fainelli
---
arch/arm64/kernel/entry.S | 2 ++
arch/arm64/kvm/hyp/entry.S | 2 ++
arch/arm64/kvm/hyp/hyp-entry.S | 4
3 files changed, 8 insertions(+)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index c1ffa95c0ad2..f70e0893ba51 100644
--- a/arch/arm64
at the point of an ERET, this could potentially be used as part of a
side-channel attack.
This patch emits an SB sequence after each ERET so that speculation is
held up on exception return.
Signed-off-by: Will Deacon
Signed-off-by: Florian Fainelli
---
arch/arm64/kernel/entry.S | 2 ++
arch
On 7/20/20 6:04 AM, Greg KH wrote:
> On Thu, Jul 09, 2020 at 12:50:23PM -0700, Florian Fainelli wrote:
>> From: Will Deacon
>>
>> commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
>>
>> Some CPUs can speculate past an ERET instruction and potentiall
]
Signed-off-by: Florian Fainelli
---
Changes in v2:
- added missing hunk in hyp/entry.S per Will's feedback
arch/arm64/kernel/entry.S | 2 ++
arch/arm64/kvm/hyp/entry.S | 2 ++
arch/arm64/kvm/hyp/hyp-entry.S | 4
3 files changed, 8 insertions(+)
diff --git a/arch/arm64/kernel
On 6/11/20 9:42 PM, Florian Fainelli wrote:
> From: Will Deacon
>
> commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
>
> Some CPUs can speculate past an ERET instruction and potentially perform
> speculative accesses to memory before processing the exception return.
&g
at the point of an ERET, this could potentially be used as part of a
side-channel attack.
This patch emits an SB sequence after each ERET so that speculation is
held up on exception return.
Signed-off-by: Will Deacon
[florian: Adjust hyp-entry.S to account for the label]
Signed-off-by: Florian
. Change kasan_pte_populate,kasan_pmd_populate,kasan_pud_populate,
kasan_pgd_populate from .meminit.text section to .init.text section.
---Reported by: Florian Fainelli
---Signed off by: Abbott Liu
Cc: Andrey Ryabinin
Co-Developed-by: Abbott Liu
Tested-by: Linus Walleij
From: Andrey Ryabinin
This patch enables the kernel address sanitizer for ARM. XIP_KERNEL has
not been tested and is therefore not allowed.
Acked-by: Dmitry Vyukov
Tested-by: Linus Walleij
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
Documentation/dev-tools/kasan.rst
From: Abbott Liu
The purpose of this patch is to provide set_ttbr0/get_ttbr0 to
kasan_init function. This makes use of the CP15 definitions added in the
previous patch.
Cc: Andrey Ryabinin
Reported-by: Marc Zyngier
Tested-by: Linus Walleij
Signed-off-by: Abbott Liu
Signed-off-by: Florian
ested-by: Linus Walleij
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/include/asm/kasan_def.h | 63
arch/arm/include/asm/memory.h| 5 +++
arch/arm/kernel/entry-armv.S | 5 ++-
arch/arm/kernel/entry-common.S | 9 +++--
ar
/memset when we copy
.data to RAM and when we clear .bss, because kasan_early_init cannot be
called before the initialization of .data and .bss.
Reported-by: Russell King - ARM Linux
Tested-by: Linus Walleij
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/include/asm
nd_pop_register read stack
memory of task.
Reported-by: Florian Fainelli
Reported-by: Marc Zyngier
Tested-by: Linus Walleij
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/boot/compressed/Makefile | 1 +
arch/arm/kernel/unwind.c | 6 +-
arch/arm/mm/Makefile
We are going to add specific accessor functions for TTBR which are
32-bit/64-bit appropriate, move all CP15 register definitions into
cp15.h where they belong.
Suggested-by: Linus Walleij
Tested-by: Linus Walleij
Signed-off-by: Florian Fainelli
---
arch/arm/include/asm/cp15.h| 57
kasan_pmd_populate,kasan_pte_populate and
kasan_pud_populate into the section .init.text.
---Reported by: Florian Fainelli
- Fixed some compile error which caused by the wrong access instruction in
arch/arm/kernel/entry-common.S.
---Reported by: kbuild test robot
- Disable instrumentation
On 1/17/20 2:13 AM, Linus Walleij wrote:
> On Tue, Nov 19, 2019 at 1:14 AM Florian Fainelli wrote:
>> On 11/15/19 3:44 AM, Marco Felsch wrote:
>>>
>>> With your v7 it is working on my imx6 but unfortunately I can't run my
>>> gstreamer testcase. My CPU load g
On 11/15/19 3:44 AM, Marco Felsch wrote:
>
> With your v7 it is working on my imx6 but unfortunately I can't run my
> gstreamer testcase. My CPU load goes to 100% after starting gstreamer
> and nothing happens.. But the test_kasan module works =) So I decided to
> check a imx6quadplus but this
Hello Marco,
On 11/14/19 10:12 AM, Marco Felsch wrote:
> Hi Florian,
>
> first of all, many thanks for your work on this series =) I picked your
> and Arnd patches to make it compilable. Now it's compiling but my imx6q
> board didn't boot anymore. I debugged the code and found that the branch
>
On 7/2/19 2:06 PM, Linus Walleij wrote:
> Hi Florian,
>
> On Tue, Jun 18, 2019 at 12:11 AM Florian Fainelli
> wrote:
>
>> Abbott submitted a v5 about a year ago here:
>>
>> and the series was not picked up since then, so I rebased it against
>> v5.2-rc4
On 7/2/19 2:03 PM, Linus Walleij wrote:
> Hi Florian!
>
> thanks for your patch!
>
> On Tue, Jun 18, 2019 at 12:11 AM Florian Fainelli
> wrote:
>
>> From: Abbott Liu
>>
>> The purpose of this patch is to provide set_ttbr0/get_ttbr0 to
>> kasan_ini
On 7/2/19 2:56 PM, Linus Walleij wrote:
> On Tue, Jun 18, 2019 at 12:11 AM Florian Fainelli
> wrote:
>
>> @@ -236,7 +236,8 @@ static int unwind_pop_register(struct unwind_ctrl_block
>> *ctrl,
>> if (*vsp >= (unsigned long *)ctrl->sp_high)
ott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/include/asm/kasan_def.h | 64
arch/arm/include/asm/memory.h| 5 +++
arch/arm/kernel/entry-armv.S | 5 ++-
arch/arm/kernel/entry-common.S | 9 +++--
arch/arm/mm/mmu.c| 7 +++-
5 fi
From: Andrey Ryabinin
This patch enable kernel address sanitizer for ARM.
Acked-by: Dmitry Vyukov
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
Documentation/dev-tools/kasan.rst | 4 ++--
arch/arm/Kconfig | 1 +
2 files changed, 3 insertions(+), 2 deletions
kasan_pte_populate,kasan_pmd_populate,kasan_pud_populate,
kasan_pgd_populate from .meminit.text section to .init.text section.
---Reported by: Florian Fainelli
---Signed off by: Abbott Liu
Cc: Andrey Ryabinin
Co-Developed-by: Abbott Liu
Reported-by: Russell King - ARM Linux
Reported
/memset when we copy
.data to RAM and when we clear .bss, because kasan_early_init can't
be called before the initialization of .data and .bss.
Reported-by: Russell King - ARM Linux
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/boot/compressed/decompress.c | 2 ++
arch/arm
-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/include/asm/cp15.h| 106 +
arch/arm/include/asm/kvm_hyp.h | 54 -
arch/arm/kvm/hyp/cp15-sr.c | 12 ++--
arch/arm/kvm/hyp/switch.c | 6 +-
4 files changed, 115 insertions
and kasan_pud_populate is in section .init.text. So
we need change kasan_pmd_populate,kasan_pte_populate and
kasan_pud_populate into the section .init.text.
---Reported by: Florian Fainelli
- Fixed some compile error which caused by the wrong access instruction in
arch/arm/kernel/entry-common.S
_register read
stack memory of task.
Reported-by: Florian Fainelli
Reported-by: Marc Zyngier
Signed-off-by: Abbott Liu
Signed-off-by: Florian Fainelli
---
arch/arm/boot/compressed/Makefile | 1 +
arch/arm/kernel/unwind.c | 3 ++-
arch/arm/mm/Makefile | 1 +
arch/arm/vdso/Mak
d support for ICC_SGI0R and
> ICC_ASGI1R accesses")
> Reported-by: Florian Fainelli
> Signed-off-by: Marc Zyngier
Tested-by: Florian Fainelli
Thanks!
--
Florian
___
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
d support for ICC_SGI0R and
> ICC_ASGI1R accesses")
> Reported-by: Florian Fainelli
> Signed-off-by: Marc Zyngier
> ---
> Paolo, Radim,
>
> Could you please send this patch directly to Greg so that it makes it
> into 4.19? I thought I had it fixed long before the merge window, an
Hi,
Seeing the following BUG_ON() being triggered on a Lamobo R1
(SUN7I/Cortex-A7), did not have the time to run a bisection since I was
chasing another regression. My guess would be that
3e8a8a50c7ef1a4f71921731f0e1748a7f70ddaa ("KVM: arm: vgic-v3: Add
support for ICC_SGI0R and ICC_ASGI1R
or all paths that a CPU re-enters the kernel.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
> Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
Something I missed, is that this correctly warns about e.g: missing the
IBE bit for secondary cores, but it seems
On 05/21/2018 04:42 AM, Russell King - ARM Linux wrote:
> This is the second posting - the original cover note is below. Comments
> from previous series addresesd:
> - Drop R7 and R8 changes.
> - Remove "PSCI" from the hypervisor version of the workaround.
>
> arch/arm/include/asm/bugs.h
A73, A75: flush BTB.
>>>> Cortex A15, Brahma B15: invalidate icache.
>>>>
>>>> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
>>>> Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
>>>> ---
>>>> arch/
he.
>
> Cortex A57 and Cortex A72 are not addressed in this patch.
>
> Cortex R7 and Cortex R8 are also not addressed as we do not enforce
> memory protection on these cores.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian F
set, and print a warning at alert level
> if this is not the case.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
--
Florian
___
kvmarm mailing lis
A9, A12, A17, A73, A75: flush BTB.
> Cortex A15, Brahma B15: invalidate icache.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
--
Florian
___
kvmarm mailing
set, and print a warning at alert level
> if this is not the case.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
I would be keen on updating arch/arm/kernel/head.S to to attempt setting
ACTRL[0]=
On 05/16/2018 04:01 AM, Russell King wrote:
> Include Brahma B15 in the Spectre v2 KVM workarounds.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
--
Florian
__
ch ever path (boot CPU, secondary CPU startup,
> CPU resuming, etc.)
>
> This allows processor specific bug checks to validate that workaround
> bits are properly enabled by firmware via all entry paths to the kernel.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.u
On 05/16/2018 04:01 AM, Russell King wrote:
> Add a Kconfig symbol for CPUs which are vulnerable to the Spectre
> attacks.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@g
or all paths that a CPU re-enters the kernel.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
> ---
> arch/arm/include/asm/bugs.h | 2 ++
> arch/arm/kernel/bugs.c | 5 +
> arch/arm/kernel/smp.c
ores */
> +#define ARM_CPU_PART_BRAHMA_B15 0x42f0
For B15:
Acked-by: Florian Fainelli <f.faine...@gmail.com>
> +
> /* DEC implemented cores */
> #define ARM_CPU_PART_SA1100 0x4400a110
>
>
--
Florian
On 05/16/2018 04:00 AM, Russell King wrote:
> Prepare the processor bug infrastructure so that it can be expanded to
> check for per-processor bugs.
>
> Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@g
On 03/18/2018 06:20 PM, Liuwenliang (Abbott Liu) wrote:
> On 03/19/2018 03:14 AM, Florian Fainelli wrote:
>> Thanks for posting these patches! Just FWIW, you cannot quite add
>> someone's Tested-by for a patch series that was just resubmitted given
>> the differences
Hi Abbott,
On 03/18/2018 05:53 AM, Abbott Liu wrote:
> Changelog:
> v2 - v1
> - Fixed some compiling error which happens on changing kernel compression
> mode to lzma/xz/lzo/lz4.
> ---Reported by: Florian Fainelli <f.faine...@gmail.com>,
>Russ
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