Hi,
On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote:
> +/**
> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior
> + * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
> + */
> + .macro pre_disable_mmu_workaround
> +#ifdef C
2017 Arm Ltd.
> +#ifndef __ASM_VMAP_STACK_H
> +#define __ASM_VMAP_STACK_H
> +
> +#include
> +#include
> +#include
> +#include
> +#include
I think we also need:
#include // for BUILD_BUG_ON()
#incldue // for IS_ENABLED()
Otherwise, this looks good to me
On Tue, Nov 28, 2017 at 04:07:26PM +0100, Andrew Jones wrote:
> Hi Mark,
Hi Drew,
> On Mon, Nov 27, 2017 at 04:38:06PM +, Mark Rutland wrote:
> > +Architecture overview
> > +-
> > +
> > +The ARMv8.3 Pointer Authentication extension adds primi
Now that all the necessary bits are in place for userspace / KVM guest
pointer authentication, add the necessary Kconfig logic to allow this to
be enabled.
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arc
Now that we've added code to support pointer authentication, add some
documentation so that people can figure out if/how to use it.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Yao Qi
---
Documentation/arm64/booting.txt| 8 +++
Documentation/
__tlb_switch_to_guest_vhe().
The now unused HCR_HOST_VHE_FLAGS definition is removed.
Signed-off-by: Mark Rutland
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 1 -
arch/arm64/include/asm/kvm_host.h | 5 -
arch/arm64
(when scheduled on a physical CPU which
supports the relevant feature). When the guest is scheduled on a
physical CPU lacking the feature, these atetmps will result in an UNDEF
being taken by the guest.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm
-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Yao Qi
---
arch/arm64/include/asm/pointer_auth.h | 8
arch/arm64/include/uapi/asm/ptrace.h | 7 +++
arch/arm64/kernel/ptrace.c| 38 +++
include/uapi/linux/elf.h
s the LR value, and not the
FP.
This only affects the in-kernel unwinder. When userspace performs
unwinding, it is up to userspace to strip PACs as necessary (which can
be determined from DWARF information).
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Yao Qi
---
arch/
is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/mmu.h | 5 ++
arch/arm64
HCR_EL2
itself.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Will Deacon
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 2 ++
arch/arm64/kernel/head.S | 19 +--
2 files changed, 19 insertions(+), 2
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.
It is assumed that if all CPUs support an IMP DEF algorithm, the same
algorithm is used across all CPUs.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm
sts and
userspace. As marking them with FTR_HIDDEN only hides them from
userspace, they are also protected with ifdeffery on
CONFIG_ARM64_POINTER_AUTHENTICATION.
Signed-off-by: Mark Rutland
Cc: Suzuki K Poulose
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Suzuki K Poulose
---
arch/arm64/ker
, allow each hook to be overridden indiviually,
by placing each under an #ifndef block. As architectures providing their
own hooks can't include this file today, this shouldn't adversely affect
any existing hooks.
Signed-off-by: Mark Rutland
Cc: Arnd Bergmann
Cc: linux-a...@vger.
rk/linux.git
arm64/pointer-auth
[4] git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
pointer-auth
Mark Rutland (12):
asm-generic: mm_hooks: allow hooks to be overridden individually
arm64: add pointer authentication register bits
arm64/cpufeature: add ARMv8.3 id_a
On Wed, Nov 01, 2017 at 08:54:44PM +0800, gengdongjiu wrote:
> On 2017/11/1 19:24, Robin Murphy wrote:
> >> + esb
> >> +alternative_else_nop_endif
> >> +1:
> >> + .endm
> > Having a branch in here is pretty horrible, and furthermore using label
> > number 1 has a pretty high chance of subtly brea
On Sat, Oct 21, 2017 at 05:18:17PM +0200, Christoffer Dall wrote:
> On Fri, Oct 20, 2017 at 05:54:40PM +0100, Mark Rutland wrote:
> > On Fri, Oct 20, 2017 at 05:53:39PM +0100, Marc Zyngier wrote:
> > > On 20/10/17 17:27, Mark Rutland wrote:
> > > > On Fri, Oct 20,
On Fri, Oct 27, 2017 at 08:59:23AM +0100, Marc Zyngier wrote:
> On Fri, Oct 27 2017 at 8:37:28 am BST, Mark Rutland
> wrote:
> > On Fri, Oct 27, 2017 at 07:57:12AM +0100, Marc Zyngier wrote:
> >> On Thu, Oct 26 2017 at 4:48:39 pm BST, Mark Rutland
> >> wrote:
On Fri, Oct 27, 2017 at 07:57:12AM +0100, Marc Zyngier wrote:
> On Thu, Oct 26 2017 at 4:48:39 pm BST, Mark Rutland
> wrote:
> > On Fri, Oct 06, 2017 at 04:34:00PM +0100, Marc Zyngier wrote:
> >> @@ -485,8 +495,21 @@ int vgic_v3_probe(const stru
Hi,
On Fri, Oct 06, 2017 at 04:34:00PM +0100, Marc Zyngier wrote:
> The GICv4 architecture doesn't prevent CPUs implementing GICv4 to
> cohabit with CPUs limited to GICv3 in the same system.
>
> This is mad (the scheduler would have to be made aware of the v4
> capability), and we're certainly no
On Fri, Oct 20, 2017 at 05:53:39PM +0100, Marc Zyngier wrote:
> Hi Mark,
>
> On 20/10/17 17:27, Mark Rutland wrote:
> > Hi Marc,
> >
> > On Fri, Oct 20, 2017 at 04:48:58PM +0100, Marc Zyngier wrote:
> >> @@ -181,18 +185,40 @@ static inline void
> &
Hi Marc,
On Fri, Oct 20, 2017 at 04:48:58PM +0100, Marc Zyngier wrote:
> @@ -181,18 +185,40 @@ static inline void
> __invalidate_icache_guest_page(struct kvm_vcpu *vcpu,
> return;
> }
>
> - /* PIPT cache. As for the d-side, use a temporary kernel mapping. */
> + /*
>
On Tue, Jul 25, 2017 at 01:06:43PM +0100, Mark Rutland wrote:
> On Fri, Jul 21, 2017 at 06:05:09PM +0100, Dave Martin wrote:
> > On Wed, Jul 19, 2017 at 05:01:21PM +0100, Mark Rutland wrote:
> > > This series adds support for the ARMv8.3 pointer authentication extension.
>
On Tue, Aug 01, 2017 at 01:00:14PM +0200, Christoffer Dall wrote:
> On Wed, Jul 19, 2017 at 05:01:31PM +0100, Mark Rutland wrote:
> > When pointer authentication is supported, a guest may wish to use it.
> > This patch adds the necessary KVM infrastructure for this to work, with
Hi,
On Tue, Jul 25, 2017 at 12:32:10PM +0100, Yao Qi wrote:
> On 19/07/17 17:01, Mark Rutland wrote:
> > If authentication fails, bits are set in the pointer such that it is
> > guaranteed to cause a fault if used.
>
> How does user space know the fault is caused b
On Tue, Jul 25, 2017 at 10:12:24PM +0800, Li Kun wrote:
> Hi Mark,
Hi,
> Could you please give us some information about the impact to
> performance to help us evaluating the influence to the system?
I'm afraid I don't have any performance details to share, as this series
has been developed and
On Tue, Jul 25, 2017 at 01:11:48PM +0100, Dave Martin wrote:
> On Mon, Apr 03, 2017 at 04:19:23PM +0100, Mark Rutland wrote:
> > +/*
> > + * The pointer bits used by a pointer authentication code.
> > + * If we were to use tagged pointers, bits 63:56 would also apply.
On Fri, Jul 21, 2017 at 06:05:09PM +0100, Dave Martin wrote:
> On Wed, Jul 19, 2017 at 05:01:21PM +0100, Mark Rutland wrote:
> > This series adds support for the ARMv8.3 pointer authentication extension.
> > Open questions
> > ==
> >
> > * Should k
, APDBKey) are disabled,
and will behave as NOPs. These may be made use of in future patches.
No support is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc
sufficient for systems with uniform pointer authentication
support. For systems with mismatched support, it will be necessary to
hide the feature from the guest's view of the ID registers.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/
Now that we've added code to support pointer authentication, add some
documentation so that people can figure out if/how to use it.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Jiong Wang
Cc: Will Deacon
Cc: Yao Qi
---
Documentation/arm64/booting.txt
__tlb_switch_to_guest_vhe().
The now unused HCR_HOST_VHE_FLAGS definition is removed.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 1 -
arch/arm64/include/asm/kvm_host.h | 5 -
arch/arm64/kvm/hyp
-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Jiong Wang
Cc: Will Deacon
Cc: Yao Qi
---
arch/arm64/include/asm/pointer_auth.h | 8 +++
arch/arm64/include/uapi/asm/ptrace.h | 5 +
arch/arm64/kernel/ptrace.c| 39 +++
include/uapi/linux/elf.h
HCR_EL2
itself.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Will Deacon
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 2 ++
arch/arm64/kernel/head.S | 19 +--
2 files changed, 19 insertions(+), 2
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.
Currently, this only detects the presence of an architected algorithm.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch
ned-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Suzuki K Poulose
---
arch/arm64/kernel/cpufeature.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9f9e0064..b23ad83 100644
--- a/a
, allow each hook to be overridden indiviually,
by placing each under an #ifndef block. As architectures providing their
own hooks can't include this file today, this shouldn't adversely affect
any existing hooks.
Signed-off-by: Mark Rutland
Cc: Arnd Bergmann
Cc: linux-a...@vger.
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm
his when unwinding with DWARF.
Thanks,
Mark.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-April/498941.html
[2] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
arm64/pointer-auth
[3] git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
pointer-auth
Mark Rutland
that developers could
refer to.
This patch adds a document describing the (native) arm64 ELF hwcaps.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Dave Martin
Cc: Suzuki K Poulose
Cc: Will Deacon
---
Documentation/arm64/elf_hwcaps.txt | 133 +
1 file ch
Almost all of the arm64 KVM code uses the sysreg mnemonics for AArch64
register descriptions. Move the last straggler over.
To match what we do for SYS_ICH_AP*R*_EL2, the SYS_ICC_AP*R*_EL1
mnemonics are expanded in .
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Christoffer Dall
Cc
] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
kvm-arm64/gicv3-cpuif-mediated-access
Mark Rutland (2):
arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1
arm64/kvm: vgic: use SYS_DESC()
arch/arm64/include/asm/arch_gicv3.h | 2 +-
arch/arm64/include/asm/sysreg.
Per ARM DDI 0487B.a, the registers are named ICC_IGRPEN*_EL1 rather than
ICC_GRPEN*_EL1. Correct our mnemonics and comments to match, before we
add more GICv3 register definitions.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Will Deacon
Cc
We've supported KVM with 16K pages since commit:
02e0b7600f835007 ("arm64: kvm: Add support for 16K pages")
... yet the kconfig text says this combination is not supported.
Let's fix that by deleting the misleading text.
Signed-off-by: Mark Rutland
Acked-by: Marc Zyng
On Tue, May 30, 2017 at 05:17:01PM +0100, Marc Zyngier wrote:
> On 03/05/17 16:58, Marc Zyngier wrote:
> > On 03/05/17 16:32, Mark Rutland wrote:
> >> On Wed, May 03, 2017 at 11:45:42AM +0100, Marc Zyngier wrote:
> >>> +static void __hyp_text __vgic
ll, let's add a set of macros that convert an ESR value into
> the corresponding sysreg encoding.
>
> We handle both AArch32 and AArch64, taking advantage of identical
> encodings between system registers and CP15 accessors.
>
> Signed-off-by: Marc Zyngier
Nice!
Acked-b
On Wed, May 03, 2017 at 11:45:42AM +0100, Marc Zyngier wrote:
> As we're about to access the Active Priority registers a lot more,
> let's define accessors that take the register number as a parameter.
>
> Signed-off-by: Marc Zyngier
> ---
> virt/kvm/arm/hyp/vgic-v3-sr.c | 116
> +++
On Fri, Apr 28, 2017 at 08:18:52AM +0100, Ard Biesheuvel wrote:
> On 27 April 2017 at 23:52, Matthias Kaehlcke wrote:
> > El Thu, Apr 27, 2017 at 12:02:56PM +0100 Mark Rutland ha dit:
> >> On Wed, Apr 26, 2017 at 02:46:16PM -0700, Matthias Kaehlcke wrote:
> >> > M
On Fri, Apr 28, 2017 at 11:20:21AM +0100, Ard Biesheuvel wrote:
> On 28 April 2017 at 10:53, Mark Rutland wrote:
> > On Fri, Apr 28, 2017 at 08:18:52AM +0100, Ard Biesheuvel wrote:
> >> On 27 April 2017 at 23:52, Matthias Kaehlcke wrote:
> >> > El Thu, Apr 27,
On Fri, Apr 28, 2017 at 08:18:52AM +0100, Ard Biesheuvel wrote:
> On 27 April 2017 at 23:52, Matthias Kaehlcke wrote:
> > El Thu, Apr 27, 2017 at 12:02:56PM +0100 Mark Rutland ha dit:
> >> On Wed, Apr 26, 2017 at 02:46:16PM -0700, Matthias Kaehlcke wrote:
> >> > -
Hi,
On Wed, Apr 26, 2017 at 02:46:16PM -0700, Matthias Kaehlcke wrote:
> Many inline assembly statements don't include the 'x' modifier when
> using xN registers as operands. This is perfectly valid, however it
> causes clang to raise warnings like this:
>
> warning: value size does not match reg
On Tue, Apr 18, 2017 at 09:32:31AM +0100, Mark Rutland wrote:
> Hi Suzuki,
>
> On Thu, Apr 13, 2017 at 04:50:46PM +0100, Suzuki K. Poulose wrote:
> > kvm: Hold reference to the user address space
> >
> > The core KVM code, uses mmgrab/mmdrop to pin the mm struct
is fine to do so, as we are doing it from the context of the same process.
>
> This also prevents the race condition where mmu_notifier_release() could
> be called in parallel and one instance could end up using a free'd kvm
> instance.
>
> Cc: Mark Rutland
> Cc: Paolo Bo
On Thu, Apr 13, 2017 at 01:53:13PM +0200, Andrey Konovalov wrote:
> On Thu, Apr 13, 2017 at 11:34 AM, Mark Rutland wrote:
> > I had a go at reproducing this on an arm64 board following [1], but so
> > far I've had no luck.
[...]
> Hi Mark,
>
> You assume that yo
Hi,
On Thu, Mar 30, 2017 at 06:31:07PM +0800, Xie XiuQi wrote:
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index f20c64a..22f9c90 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -106,6 +106,20 @@
> #define ESR_ELx_AR
On Wed, Apr 12, 2017 at 08:51:31PM +0200, Andrey Konovalov wrote:
> On Wed, Apr 12, 2017 at 8:43 PM, Marc Zyngier wrote:
> > On 12/04/17 17:19, Andrey Konovalov wrote:
> >> I now have a way to reproduce it, so I can test proposed patches. I
> >> don't have a simple C reproducer though.
> >>
> >>
being available (e.g. as we expect for FP and other
things today). I'm not sure quite what to say, and as it stands this
isn't quite correct.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
---
Documentation/arm64/booting.txt| 8 +++
Documentatio
, we cannot
determine whether userspace is making use of the feature, so debuggers
need to cope with this case regardless.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Jiong Wang
Cc: Will Deacon
---
arch/arm64/include/asm/pointer_auth.h | 8 +++
arch/arm64/include/uapi/asm/ptrace.h
need to trap accesses to these to provide
santized values.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_emulate.h | 15 +
arch/arm64/include/asm/kvm_host.h| 12 ++
arch/arm64/kvm/hyp
, APDBKey) are disabled,
and will behave as NOPs. These may be made use of in future patches.
No support is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc
HCR_EL2
itself.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Will Deacon
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_arm.h | 2 ++
arch/arm64/kernel/head.S | 19 +--
2 files changed, 19 insertions(+), 2
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.
Currently, this only detects the presence of an architected algorithm.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch
, allow each hook to be overridden indiviually,
by placing each under an #ifndef block. As architectures providing their
own hooks can't include this file today, this shouldn't adversely affect
any existing hooks.
Signed-off-by: Mark Rutland
Cc: Arnd Bergmann
Cc: linux-a...@vger.
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm
ned-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/kernel/cpufeature.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 81a78d9..30255b2 100644
--- a/a
rm64/pointer-auth
[3] git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
pointer-auth
Mark Rutland (9):
asm-generic: mm_hooks: allow hooks to be overridden individually
arm64: add pointer authentication register bits
arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits
arm64
@vger.kernel.org # v3.10+
> Cc: Paolo Bonzini
> Cc: Marc Zyngier
> Cc: Christoffer Dall
> Cc: Mark Rutland
> Signed-off-by: Suzuki K Poulose
> [ Avoid vCPU starvation and lockup detector warnings ]
> Signed-off-by: Marc Zyngier
> Signed-off-by: Suzuki K Poulose
>
&g
On Thu, Mar 30, 2017 at 03:31:12PM +0100, Mark Rutland wrote:
> Hi,
>
> I'm seeing the splat below when running KVM on an arm64 host with
> CONFIG_DEBUG_ATOMIC_SLEEP and CONFIG_LOCKDEP enabled.
>
> I saw this on v4.11-rc1, and I can reproduce the problem on the current
Hi,
I'm seeing the splat below when running KVM on an arm64 host with
CONFIG_DEBUG_ATOMIC_SLEEP and CONFIG_LOCKDEP enabled.
I saw this on v4.11-rc1, and I can reproduce the problem on the current
kvmarm master branch (563e2f5daa66fbc1).
I've hacked noinlines into arch/arm/kvm/mmu.c in an attempt
On Wed, Mar 29, 2017 at 09:41:47AM +0100, Will Deacon wrote:
> On Tue, Mar 28, 2017 at 10:29:31PM +0200, Christoffer Dall wrote:
> > On Tue, Mar 28, 2017 at 07:48:28PM +0100, Mark Rutland wrote:
> > > On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote:
> > >
On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote:
> On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote:
> > On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote:
>
> > > The next question is how do we merge this. Obviously, we can't split i
Hi Daniel,
On Thu, Mar 23, 2017 at 06:42:01PM +0100, Daniel Lezcano wrote:
> In the next changes, we track the interrupts but we discard the timers as
> that does not make sense. The next interrupt on a timer is predictable.
Sorry, but I could not parse this.
[...]
> diff --git a/drivers/perf/
Hi,
On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote:
> On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote:
> > The next question is how do we merge this. Obviously, we can't split it
> > between trees, and this is very likely to clash with anything that we
> > will merge on
On Wed, Mar 15, 2017 at 03:06:33PM +0100, Andrew Jones wrote:
> On Wed, Mar 15, 2017 at 02:36:45PM +0100, Christoffer Dall wrote:
> > > If QEMU wants to know
> > > whether or not the host it's running on is heterogeneous, then
> > > it can just query sysfs, rather than ask KVM.
> > >
> >
> > Can
On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote:
> On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote:
> > On Thu, Mar 09 2017 at 5:07:12 pm GMT, Mark Rutland
> > wrote:
> > The next question is how do we merge this. Obviously, we can't split it
&
On Thu, Mar 09, 2017 at 09:25:12AM +0100, Ard Biesheuvel wrote:
> +static inline u64 pte_cont_addr_end(u64 addr, u64 end)
> +{
> + return min((addr + CONT_PTE_SIZE) & CONT_PTE_MASK, end);
> +}
> +
> +static inline u64 pmd_cont_addr_end(u64 addr, u64 end)
> +{
> + return min((addr + CONT_PMD
lags = NO_BLOCK_MAPPINGS;
> +
> __create_pgd_mapping(mm->pgd, phys, virt, size, prot,
> - pgd_pgtable_alloc, page_mappings_only);
> + pgd_pgtable_alloc, flags);
> }
Given we can't pass the flags in to create_pgd_mappin
>
> Signed-off-by: Ard Biesheuvel
Reviewed-by: Mark Rutland
Strictly speaking, I think this is marginally more stringent than what
the ARM ARM describes. My reading is that the "Misprogramming of the
Contiguous bit" rules only apply when there are multiple valid entries,
and h
ically in use by the kernel image.
>
> Signed-off-by: Ard Biesheuvel
This makes sense to me, and I haven't found anything this breaks.
It may be worth noting that a similar reasoning already applies the the
FDT mapping, where we use create_mapping_noalloc(), and never mandate
page map
This patch adds sysreg definitions for system registers in the debug and
trace system register encoding space. Subsequent patches will make use
of these definitions.
The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-5.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc
is applied to bring these into line with the usual comment style.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/kvm/sys_regs.c | 78 +--
1 file changed, 22 insertions(+), 56 deletions
are only made for
registers used today by KVM.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/sysreg.h | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/include
Now that we have common definitions for the encoding of Set/Way cache
maintenance operations, make the KVM code use these, simplifying the
sys_reg_descs table.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/kvm/sys_regs.c | 12
Now that we have common definitions for the physical timer control
registers, make the KVM code use these, simplifying the sys_reg_descs
table.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/kvm/sys_regs.c | 12 +++-
1
document.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/sysreg.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
Now that we have common definitions for the remaining register encodings
required by KVM, make the KVM code use these, simplifying the
sys_reg_descs table and the genericv8_sys_regs table.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
This patch adds a macro enabling us to initialise sys_reg_desc
structures based on common sysreg encoding definitions in
. Subsequent patches will use this to simplify the KVM
code.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch
Now that we have common definitions for the register encodings used by
KVM, make the KVM code uses thse for invariant sysreg definitions. This
makes said definitions a reasonable amount shorter, especially as many
comments are rendered redundant and can be removed.
Signed-off-by: Mark Rutland
Cc
-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/kvm/sys_regs.c | 73 ++-
1 file changed, 21 insertions(+), 52 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
registers, and
to allow us to change the way these are handled in future, a new
sys_insn() alias for sys_reg() is added and used for these new
definitions.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/sysreg.h | 6
Now that we have common definitions for the GICv3 register encodings,
make the KVM code use these, simplifying the sys_reg_descs table.
Signed-off-by: Mark Rutland
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/kvm/sys_regs.c | 8 ++--
1 file changed
conflicts.
This patch enforces this order, by moving the few items that break it.
There should be no functional change.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/sysreg.h | 17 +
1 file changed
This patch adds sysreg definitions for system registers used to control
the architected physical timer. Subsequent patches will make use of
these definitions.
The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-6.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
this patch moves the definitions to ,
adding a SYS_ prefix, and sorting the registers per their encoding.
Existing users of the definitions are fixed up so that this change is
not problematic.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: Will Deacon
* Rebase to v4.11-rc1, solving a trivial conflict.
* Handle the physical counter registers.
* Verified section differences again.
Thanks,
Mark.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
arm64/common-sysreg
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-Janu
- pfn++;
> + set_pte(pte, pfn_pte(__phys_to_pfn(phys), prot));
> + phys += PAGE_SIZE;
Minor nit: so as to align the strucutre of the loop with the other
functions, it'd be nice to have this on the final line of the loop body.
Either way:
Reviewed-b
On Thu, Mar 09, 2017 at 04:52:18AM -0800, Christoffer Dall wrote:
> On Mon, Jan 16, 2017 at 05:33:34PM +0800, Shannon Zhao wrote:
> > From: Shannon Zhao
> >
> > Check if the configuration is fine.
>
> This commit message really needs some love and attention.
>
> >
> > Signed-off-by: Shannon Zh
On Wed, Mar 08, 2017 at 11:57:22AM +0100, Ard Biesheuvel wrote:
> On 7 March 2017 at 17:46, Mark Rutland wrote:
> > Note that I've cheated and made alloc_init_pte() take a phys_addr_t
> > rather than a pfn, which I think we should do anyhow for consistency. I
> > hav
Hi,
On Sat, Mar 04, 2017 at 02:30:48PM +, Ard Biesheuvel wrote:
> This is the third attempt at enabling the use of contiguous hints for
> kernel mappings. The most recent attempt 0bfc445dec9d was reverted after
> it turned out that updating permission attributes on live contiguous ranges
> may
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