On Mon, Jul 18, 2022 at 08:26:14AM -0700, Kalesh Singh wrote:
> On Mon, Jul 18, 2022 at 5:52 AM Russell King (Oracle)
> wrote:
> >
> > Hi,
> >
> > Can you please explain why you are targetting my @oracle.com email
> > address with this patch set?
> >
>
Hi,
Can you please explain why you are targetting my @oracle.com email
address with this patch set?
This causes me problems as I use Outlook's Web interface for that
which doesn't appear to cope with the threading, and most certainly
is only capable of top-reply only which is against Linux
o trap on those register
> accesses in EL1. Do not set this bit until the whole nesting support is
Maybe:
, but will be done in a future patch once nested support
is complete.
> completed.
>
> Signed-off-by: Jintack Lim
> Signed-off-by: Marc Zyngier
Reviewed-by: Rus
ped
> accesses to these registers.
>
> Signed-off-by: Christoffer Dall
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
_
e the reverse translation as an
inline function after the above too, so the two translations are
together - but as it's only used (in this patch at least) in switch.c
there probably isn't too much point.
So:
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/
te.
>
> Yes, this is slow. Don't do it.
I'd hope this is very unlikely!
>
> Suggested-by: Alexandru Elisei
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up.
n order to make sure that accesses to the virtual
> view of SPSR_EL2 is correct.
>
> To do so, we place an illegal value in SPSR_EL1.M, and patch it
> accordingly if required when accessing it.
>
> Reviewed-by: Alexandru Elisei
> Signed-off-by: Marc Zyngier
Reviewed-by: Rus
d-by: Ganapatrao Kulkarni
> Reviewed-by: Alexandru Elisei
> Co-developed-by: Andre Przywara
> Signed-off-by: Andre Przywara
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps
ects non-VHE guest hypervisors, as VHE system registers
> are compatible with the EL1 counterparts.
>
> These helpers will get used in subsequent patches.
>
> Co-developed-by: Andre Przywara
> Signed-off-by: Andre Przywara
> Signed-off-by: Marc Zyngier
Reviewed-by: Russ
Jintack Lim
> [maz: EL2_REG() macros]
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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gt; This will be used to support nested virtualization in KVM.
>
> Signed-off-by: Jintack Lim
> Signed-off-by: Andre Przywara
> Signed-off-by: Christoffer Dall
> [maz: moved the command-line option to kvm-arm.mode]
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (
urn in software.
>
> Signed-off-by: Christoffer Dall
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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the virtual EL2)
> are supposed to handled in the virtual EL2.
>
> Forward these to EL2 as required.
>
> Signed-off-by: Jintack Lim
> [maz: add handling of HCR_EL2.HCD]
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/handle_exit.c | 11 +++
Reviewed-by: Russell Kin
On Mon, Nov 29, 2021 at 08:00:55PM +, Marc Zyngier wrote:
> From: Jintack Lim
>
> Support injecting exceptions and performing exception returns to and
> from virtual EL2. This must be done entirely in software except when
> taking an exception from vEL0 to vEL2 when the virtual
>
> Signed-off-by: Christoffer Dall
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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kv
On Mon, Nov 29, 2021 at 08:00:53PM +, Marc Zyngier wrote:
> From: Jintack Lim
>
> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
> this bit is set, accessing EL2 registers in EL1 traps to EL2. In
> addition, executing the following instructions in EL1 will trap to
convenient primitives for this.
>
> Signed-off-by: Christoffer Dall
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps u
On Mon, Nov 29, 2021 at 08:00:51PM +, Marc Zyngier wrote:
> Add the minimal set of EL2 system registers to the vcpu context.
> Nothing uses them just yet.
>
> Reviewed-by: Andre Przywara
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patc
-by: Christoffer Dall
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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kvmarm mailing list
kvma
empty data structures]
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
However, a couple of comments below.
> ---
> arch/arm64/kvm/reset.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kvm/reset.c b/arch
ems without nested virt enabled
> should have neglgible overhead.
>
> We don't yet allow userspace to actually set this feature.
>
> Signed-off-by: Christoffer Dall
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.arm
encoding).
>
> Propagate the SW bits specified by the caller, and store them into
> the corresponding entry.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps
rao Kulkarni
> Reviewed-by: Ganapatrao Kulkarni
> Signed-off-by: Marc Zyngier
Looks fairly simple.
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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__
.
>
> Reviewed-by: Alexandru Elisei
> Tested-by: Alexandru Elisei
> Signed-off-by: Marc Zyngier
> Link: https://lore.kernel.org/r/20211126115533.217903-1-...@kernel.org
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FT
ewed-by: Fuad Tabba
> Signed-off-by: Marc Zyngier
Reviewed-by: Russell King (Oracle)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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kvmarm mailing lis
On Mon, Nov 29, 2021 at 08:00:43PM +, Marc Zyngier wrote:
> diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c
> b/arch/arm64/kvm/hyp/nvhe/switch.c
> index c0e3fed26d93..d13115a12434 100644
> --- a/arch/arm64/kvm/hyp/nvhe/switch.c
> +++ b/arch/arm64/kvm/hyp/nvhe/switch.c
> @@ -233,7 +233,7 @@
ested
> it on the M1 (which really doesn't have an architectural PMU) to
> verify that it was correctly failing.
My test program that derives the number of registers qemu uses now
reports 236 registers again and I see:
kvm [7]: PMU detected and enabled
in the kernel boot log.
Tested-by:
Hi,
This morning, I upgraded my VM host from Debian Buster to Debian
Bullseye. This host (Armada 8040) runs libvirt. I placed all the VMs
into managedsave, which basically means their state is saved out by
QEMU ready to be resumed once the upgrade is complete.
Initially, I was running 5.11 on
block_find_in_range() private method of memblock.
>
> This simplifies the callers, ensures that (unlikely) errors in
> memblock_reserve() are handled and improves maintainability of
> memblock_find_in_range().
>
> Signed-off-by: Mike Rapoport
Acked-by: Russell
On Fri, Jul 30, 2021 at 01:40:39PM +0300, Mike Rapoport wrote:
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index f97eb2371672..1f8ef9fd5215 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -1012,31 +1012,25 @@ static void __init
On Tue, Jul 13, 2021 at 04:59:58PM +0100, Marc Zyngier wrote:
> On Tue, 13 Jul 2021 15:39:49 +0100,
> "Russell King (Oracle)" wrote:
> >
> > On Tue, Jul 13, 2021 at 02:58:58PM +0100, Marc Zyngier wrote:
> > > +static void reset_pmu_reg(struct kvm_vcpu *vcpu
On Tue, Jul 13, 2021 at 02:58:58PM +0100, Marc Zyngier wrote:
> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc
> *r)
> +{
> + u64 n, mask;
> +
> + /* No PMU available, any PMU reg may UNDEF... */
> + if (!kvm_arm_support_pmu_v3())
> + return;
>
On Tue, Jun 08, 2021 at 05:48:05PM +0200, Jean-Philippe Brucker wrote:
> * Untested for AArch32 guests.
That really needs testing; you may notice Will Deacon has been
posting patches for aarch32 guests over the last few months, and
there are other users out there who run aarch32 guests on their
On Tue, Dec 29, 2020 at 04:00:59PM +, David Brazdil wrote:
> The KVM/arm64 PSCI relay assumes that SYSTEM_OFF and SYSTEM_RESET should
> not return, as dictated by the PSCI spec. However, there is firmware out
> there which breaks this assumption, leading to a hyp panic. Make KVM
> more robust
On Sun, Feb 16, 2020 at 10:18:30AM +0200, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Hi,
>
> These patches convert several architectures to use page table folding and
> remove __ARCH_HAS_5LEVEL_HACK along with include/asm-generic/5level-fixup.h.
>
> The changes are mostly about mechanical
On Mon, Feb 10, 2020 at 04:25:23PM +, Russell King - ARM Linux admin wrote:
> On Mon, Feb 10, 2020 at 02:13:19PM +, Marc Zyngier wrote:
> > KVM/arm was merged just over 7 years ago, and has lived a very quiet
> > life so far. It mostly works if you're prepared t
On Mon, Feb 10, 2020 at 02:13:19PM +, Marc Zyngier wrote:
> KVM/arm was merged just over 7 years ago, and has lived a very quiet
> life so far. It mostly works if you're prepared to deal with its
> limitations, it has been a good prototype for the arm64 version,
> but it suffers a few
On Sun, Jan 19, 2020 at 05:43:27PM +, Marc Zyngier wrote:
> On Sat, 28 Dec 2019 11:57:14 +
> Russell King wrote:
>
> > Booting 5.4 on LX2160A reveals that KVM is non-functional:
> >
> > kvm: Limiting the IPA size due to kernel Virtual Address limit
> >
size due to kernel Virtual Address limit
kvm [1]: IPA Size Limit: 43bits
kvm [1]: IDMAP page: 81a24000
kvm [1]: HYP VA range: 40:62
...
kvm [1]: Hyp mode initialized successfully
Signed-off-by: Russell King
---
arch/arm64/kvm/va_layout.c | 44
On Fri, Dec 27, 2019 at 11:47:35AM +, Russell King wrote:
> Booting 5.4 on LX2160A reveals that KVM is non-functional:
>
> kvm: Limiting the IPA size due to kernel Virtual Address limit
> kvm [1]: IPA Size Limit: 43bits
> kvm [1]: IDMAP intersecting with HYP VA, unable to co
size due to kernel Virtual Address limit
kvm [1]: IPA Size Limit: 43bits
kvm [1]: IDMAP page: 81a24000
kvm [1]: HYP VA range: 40:62
...
kvm [1]: Hyp mode initialized successfully
Signed-off-by: Russell King
---
arch/arm64/kvm/va_layout.c | 22 +++---
1 file changed
On Sun, Oct 14, 2018 at 09:21:23PM +0800, Tianyu Lan wrote:
> Sorry to confuse your. I get from CCers from get_maintainer.pl script.
Unfortunately you seem to have made a mistake. My email address is
'li...@armlinux.org.uk' not 'li...@armlinux.org'. There is no
'li...@armlinux.org' in
On Sun, Oct 14, 2018 at 10:27:34AM +0100, Russell King - ARM Linux wrote:
> On Sun, Oct 14, 2018 at 10:16:56AM +0200, Thomas Gleixner wrote:
> > On Sun, 14 Oct 2018, Liran Alon wrote:
> > > > On 13 Oct 2018, at 17:53, lantianyu1...@gmail.com wrote:
> > &g
On Sun, Oct 14, 2018 at 10:16:56AM +0200, Thomas Gleixner wrote:
> On Sun, 14 Oct 2018, Liran Alon wrote:
> > > On 13 Oct 2018, at 17:53, lantianyu1...@gmail.com wrote:
> > >
> > > From: Lan Tianyu
> > >
> > > This patch is to add wrapper functions for tlb_remote_flush_with_range
> > >
On Thu, May 31, 2018 at 11:07:18AM +0100, Marc Zyngier wrote:
> > I notice that you haven't replied to some of the patches (7 and 8),
> > which makes me think that you have an issue with them - and as tonight
> > is likely the last linux-next before the merge window, we're basically
> > out of
On Tue, May 29, 2018 at 06:02:28PM +0100, Marc Zyngier wrote:
> On Tue, 29 May 2018 15:55:01 +0100,
> Russell King wrote:
> >
> > Warn at error level if the context switching function is not what we
> > are expecting. This can happen with big.Little systems, which we
>
FFS, yes, there's a build error in this. It's an obvious fix. I
won't be re-posting it for a third time today for such a trivial
change, but I'll fix up my local version.
On Tue, May 29, 2018 at 03:53:21PM +0100, Russell King - ARM Linux wrote:
> Sorry for another version so soon af
Report support for SMCCC_ARCH_WORKAROUND_1 to KVM guests for affected
CPUs.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_host.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm
-by: Marc Zyngier
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_mmu.h | 5 +
arch/arm/kvm/hyp/hyp-entry.S | 24
2 files changed, 29 insertions(+)
diff --git a/arch/arm/include/asm/kvm_mmu.h b
this useful.
Signed-off-by: Marc Zyngier
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_asm.h | 2 --
arch/arm/include/asm/kvm_mmu.h | 17 +-
arch/arm/kvm/hyp/hyp-entry.S | 71
Warn at error level if the context switching function is not what we
are expecting. This can happen with big.Little systems, which we
currently do not support.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/proc-v7-bugs.c | 15
icache.
If the IBE bit is not set, then there is little point to enabling the
workaround.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/cp15.h| 3 ++
arch/arm/include/asm/system_misc.h | 15
arch/arm/mm/fault.c
.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/Makefile | 2 +-
arch/arm/mm/proc-v7-bugs.c | 36
arch/arm/mm/proc-v7.S | 4 ++--
3 files changed, 39 insertions
R7 and Cortex R8 are also not addressed as we do not enforce
memory protection on these cores.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/Kconfig | 19 +++
arch/arm/mm/proc-v7-2level.S | 6 ---
arch/arm/mm/proc-v7.S
.)
This allows processor specific bug checks to validate that workaround
bits are properly enabled by firmware via all entry paths to the kernel.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/proc
Add a Kconfig symbol for CPUs which are vulnerable to the Spectre
attacks.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mm/Kconfig b
Check for CPU bugs when secondary processors are being brought online,
and also when CPUs are resuming from a low power mode. This gives an
opportunity to check that processor specific bug workarounds are
correctly enabled for all paths that a CPU re-enters the kernel.
Signed-off-by: Russell
Prepare the processor bug infrastructure so that it can be expanded to
check for per-processor bugs.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/bugs.h | 4 ++--
arch/arm/kernel/Makefile| 1
Add CPU part numbers for Cortex A53, A57, A72, A73, A75 and the
Broadcom Brahma B15 CPU.
Signed-off-by: Russell King
Acked-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/cputype.h | 8
1 file changed, 8 insertions(+)
diff
insertions(+), 50 deletions(-)
create mode 100644 arch/arm/kernel/bugs.c
create mode 100644 arch/arm/mm/proc-v7-bugs.c
On Tue, May 29, 2018 at 10:07:57AM +0100, Russell King - ARM Linux wrote:
> Fourth version:
> - Only warn once per CPU about incorrect IBE bit
> (this avoids spamming t
We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible.
So let's intercept it as early as we can by testing for the
function call number as soon as we've identified a HVC call
coming from the guest.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
Report support for SMCCC_ARCH_WORKAROUND_1 to KVM guests for affected
CPUs.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_host.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm
-by: Marc Zyngier
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_mmu.h | 5 +
arch/arm/kvm/hyp/hyp-entry.S | 24
2 files changed, 29 insertions(+)
diff --git a/arch/arm/include/asm/kvm_mmu.h b
this useful.
Signed-off-by: Marc Zyngier
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_asm.h | 2 --
arch/arm/include/asm/kvm_mmu.h | 17 +-
arch/arm/kvm/hyp/hyp-entry.S | 71
Include Brahma B15 in the Spectre v2 KVM workarounds.
Signed-off-by: Russell King
Acked-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/kvm_mmu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch
Warn at error level if the context switching function is not what we
are expecting. This can happen with big.Little systems, which we
currently do not support.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/proc-v7-bugs.c | 15
Add firmware based hardening for cores that require more complex
handling in firmware.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/proc-v7-bugs.c | 64 +-
arch/arm/mm/proc-v7.S | 21
R7 and Cortex R8 are also not addressed as we do not enforce
memory protection on these cores.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/Kconfig | 19 +++
arch/arm/mm/proc-v7-2level.S | 6 ---
arch/arm/mm/proc-v7.S
icache.
If the IBE bit is not set, then there is little point to enabling the
workaround.
Signed-off-by: Russell King
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/cp15.h| 3 ++
arch/arm/include/asm/system_misc.h | 15
arch/arm/mm/fault.c
.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/Makefile | 2 +-
arch/arm/mm/proc-v7-bugs.c | 32
arch/arm/mm/proc-v7.S | 4 ++--
3 files changed, 35 insertions(+), 3
Add a Kconfig symbol for CPUs which are vulnerable to the Spectre
attacks.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/mm/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mm/Kconfig b
.)
This allows processor specific bug checks to validate that workaround
bits are properly enabled by firmware via all entry paths to the kernel.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/proc
Check for CPU bugs when secondary processors are being brought online,
and also when CPUs are resuming from a low power mode. This gives an
opportunity to check that processor specific bug workarounds are
correctly enabled for all paths that a CPU re-enters the kernel.
Signed-off-by: Russell
Prepare the processor bug infrastructure so that it can be expanded to
check for per-processor bugs.
Signed-off-by: Russell King
Reviewed-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/bugs.h | 4 ++--
arch/arm/kernel/Makefile| 1
Add CPU part numbers for Cortex A53, A57, A72, A73, A75 and the
Broadcom Brahma B15 CPU.
Signed-off-by: Russell King
Acked-by: Florian Fainelli
Boot-tested-by: Tony Lindgren
Reviewed-by: Tony Lindgren
---
arch/arm/include/asm/cputype.h | 8
1 file changed, 8 insertions(+)
diff
insertions(+), 50 deletions(-)
create mode 100644 arch/arm/kernel/bugs.c
create mode 100644 arch/arm/mm/proc-v7-bugs.c
On Fri, May 25, 2018 at 02:59:39PM +0100, Russell King - ARM Linux wrote:
> Third version:
> - Remove "PSCI" from the SMC version of the workaround as well.
>
On Fri, May 25, 2018 at 08:47:42AM -0700, Tony Lindgren wrote:
> * Russell King <rmk+ker...@armlinux.org.uk> [180525 15:10]:
> > +static void cpu_v7_spectre_init(void)
> > +{
> > + const char *spectre_v2_method = NULL;
> > + int cpu = smp_processo
Report support for SMCCC_ARCH_WORKAROUND_1 to KVM guests for affected
CPUs.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/include/asm/kvm_host.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/kvm_host.h b/ar
We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible.
So let's intercept it as early as we can by testing for the
function call number as soon as we've identified a HVC call
coming from the guest.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/kvm/h
Include Brahma B15 in the Spectre v2 KVM workarounds.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Acked-by: Florian Fainelli <f.faine...@gmail.com>
---
arch/arm/include/asm/kvm_mmu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/kvm_mmu.
e only two ARM
cores on which this useful.
Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/include/asm/kvm_asm.h | 2 --
arch/arm/include/asm/kvm_mmu.h | 17 +-
arch/arm/kvm/hyp/
Warn at error level if the context switching function is not what we
are expecting. This can happen with big.Little systems, which we
currently do not support.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/mm/proc-v7-bugs.c | 15 +++
1 file chang
icache.
If the IBE bit is not set, then there is little point to enabling the
workaround.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/include/asm/cp15.h| 3 ++
arch/arm/include/asm/system_misc.h | 15
arch/arm/mm/fault.c| 3 ++
arch/
vector decoding.
Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/include/asm/kvm_mmu.h | 5 +
arch/arm/kvm/hyp/hyp-entry.S | 24
2 files changed, 29 insertions(+)
diff --git a/ar
Add firmware based hardening for cores that require more complex
handling in firmware.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/mm/proc-v7-bugs.c | 64 +-
arch/arm/mm/proc-v7.S | 21 +++
2 files chang
.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
---
arch/arm/mm/Makefile | 2 +-
arch/arm/mm/proc-v7-bugs.c | 29 +
arch/arm/mm/proc-v7.S | 4 ++--
3 files changed, 32 insertions(+),
R7 and Cortex R8 are also not addressed as we do not enforce
memory protection on these cores.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
arch/arm/mm/Kconfig | 19 +++
arch/arm/mm/proc-v7-2level.S | 6 ---
arch/arm/mm/proc-v7.S
Add a Kconfig symbol for CPUs which are vulnerable to the Spectre
attacks.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
---
arch/arm/mm/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mm/Kconfi
Check for CPU bugs when secondary processors are being brought online,
and also when CPUs are resuming from a low power mode. This gives an
opportunity to check that processor specific bug workarounds are
correctly enabled for all paths that a CPU re-enters the kernel.
Signed-off-by: Russell
Prepare the processor bug infrastructure so that it can be expanded to
check for per-processor bugs.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
---
arch/arm/include/asm/bugs.h | 4 ++--
arch/arm/kernel/Makefile| 1
arm/kernel/bugs.c
create mode 100644 arch/arm/mm/proc-v7-bugs.c
On Mon, May 21, 2018 at 12:42:38PM +0100, Russell King - ARM Linux wrote:
> This is the second posting - the original cover note is below. Comments
> from previous series addresesd:
> - Drop R7 and R8 changes.
>
On Fri, May 25, 2018 at 11:03:59AM +0100, Russell King - ARM Linux wrote:
> On Thu, May 24, 2018 at 04:30:40PM -0700, Florian Fainelli wrote:
> > On 05/21/2018 04:44 AM, Russell King wrote:
> > > Check for CPU bugs when secondary processors are being brought online,
> &
On Thu, May 24, 2018 at 04:18:30PM -0700, Florian Fainelli wrote:
> On 05/21/2018 04:42 AM, Russell King - ARM Linux wrote:
> > This is the second posting - the original cover note is below. Comments
> > from previous series addresesd:
> > - Drop R7 and R8 changes.
>
On Thu, May 24, 2018 at 01:49:51PM +0100, Marc Zyngier wrote:
> On 24/05/18 13:30, Russell King - ARM Linux wrote:
> > On Thu, May 24, 2018 at 01:03:50PM +0100, Marc Zyngier wrote:
> >> On 23/05/18 20:45, Russell King - ARM Linux wrote:
> >>> On Tue, May 22, 2018 at
On Thu, May 24, 2018 at 01:03:50PM +0100, Marc Zyngier wrote:
> On 23/05/18 20:45, Russell King - ARM Linux wrote:
> > On Tue, May 22, 2018 at 06:24:13PM +0100, Marc Zyngier wrote:
> >> On 21/05/18 12:45, Russell King wrote:
> >>> +#ifdef CONFIG_ARM_PSCI
>
On Tue, May 22, 2018 at 06:24:13PM +0100, Marc Zyngier wrote:
> On 21/05/18 12:45, Russell King wrote:
> > +#ifdef CONFIG_ARM_PSCI
> > + if (psci_ops.smccc_version != SMCCC_VERSION_1_0) {
> > + struct arm_smccc_res res;
> > +
> > +
On Tue, May 22, 2018 at 06:15:02PM +0100, Marc Zyngier wrote:
> On 21/05/18 12:45, Russell King wrote:
> > + switch (read_cpuid_part()) {
> > + case ARM_CPU_PART_CORTEX_A8:
> > + case ARM_CPU_PART_CORTEX_A9:
> > + case ARM_CPU_PART_CORTEX_A12:
> >
On Tue, May 22, 2018 at 06:56:03PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 22, 2018 at 06:15:02PM +0100, Marc Zyngier wrote:
> > On 21/05/18 12:45, Russell King wrote:
> > > In order to prevent aliasing attacks on the branch predictor,
> > > invalidate t
On Tue, May 22, 2018 at 06:24:13PM +0100, Marc Zyngier wrote:
> On 21/05/18 12:45, Russell King wrote:
> > Add PSCI based hardening for cores that require more complex handling in
> > firmware.
> >
> > Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
>
On Tue, May 22, 2018 at 06:15:02PM +0100, Marc Zyngier wrote:
> On 21/05/18 12:45, Russell King wrote:
> > In order to prevent aliasing attacks on the branch predictor,
> > invalidate the BTB or instruction cache on CPUs that are known to be
> > affected when taking
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