From: Vijaya Kumar K
Update error code returned for Invalid CPU interface register
value and access in AArch32 mode.
Signed-off-by: Vijaya Kumar K
---
Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm/include/uapi/asm/kvm.h | 6 +
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
It is used to identify the cpu for registers access.
The VM that supports SEIs expect it on des
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
Documentation/virtual/kvm/devices/arm-vgic-v3.txt
The patch 3 & 4 are picked from the Pavel's pr
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
Reviewed-by: Eric Auger
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 i
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
On Mon, Jan 23, 2017 at 4:50 PM, Christoffer Dall
wrote:
> On Mon, Jan 23, 2017 at 04:22:39PM +0530, Vijay Kilari wrote:
>> Hi Christoffer,
>>
>> In the document,
>>
>> The mpidr field is used to specify which
>> redistributor is accessed. T
Hi Eric,
On Tue, Dec 6, 2016 at 7:23 PM, Auger Eric wrote:
> Hi,
> On 23/11/2016 14:01, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
>> ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
>>
>> Signed-off-by: Vijaya Kum
Hi Christoffer,
In the document,
The mpidr field is used to specify which
redistributor is accessed. The mpidr is ignored for the distributor.
We still rely on MPIDR for KVM_DEV_ARM_VGIC_GRP_DIST_REGS to fetch
vcpu info. So don't we need to remove this restriction?.
Or force to use vcpu
On Sat, Jan 21, 2017 at 1:29 AM, Christoffer Dall
wrote:
> Hi Vijaya,
>
> On Thu, Dec 01, 2016 at 12:39:39PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> This patchset adds API for saving and restoring
>> of VGICv3 registers to support live migration with new vgic feature.
>
On Fri, Dec 16, 2016 at 5:55 PM, Auger Eric wrote:
> Hi Vijaya,
>
> On 01/12/2016 08:09, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The cpu MPIDR va
On Tue, Dec 6, 2016 at 5:12 PM, Auger Eric wrote:
> Hi,
>
> On 28/11/2016 14:05, Christoffer Dall wrote:
>> On Wed, Nov 23, 2016 at 06:31:48PM +0530, vijay.kil...@gmail.com wrote:
>>> From: Vijaya Kumar K
>>>
>>> Read and write of some registers like ISPENDR and ICPENDR
>>> from userspace require
From: Vijaya Kumar K
Update error code returned for Invalid CPU interface register
value and access in AArch32 mode.
Signed-off-by: Vijaya Kumar K
---
Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/vir
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The VM that supports SEIs expect it on destin
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm/include/uapi/asm/kvm.h | 7 ++
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
Documentation/virtual/kvm/devices/arm-vgic-v3.txt
The patch 3 & 4 are picked from the Pavel's pr
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
On Tue, Nov 29, 2016 at 1:20 AM, Christoffer Dall
wrote:
> On Wed, Nov 23, 2016 at 06:31:54PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> Userspace requires to store and restore of line_level for
>> level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
>>
On Tue, Nov 29, 2016 at 2:07 PM, Christoffer Dall
wrote:
> On Tue, Nov 29, 2016 at 01:08:26PM +0530, Vijay Kilari wrote:
>> On Tue, Nov 29, 2016 at 1:09 AM, Christoffer Dall
>> wrote:
>> > On Wed, Nov 23, 2016 at 06:31:53PM +0530, vijay.kil...@gmail.com wrote:
&g
On Tue, Nov 29, 2016 at 1:09 AM, Christoffer Dall
wrote:
> On Wed, Nov 23, 2016 at 06:31:53PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register
From: Vijaya Kumar K
Update error code returned for Invalid CPU interface register
value.
Signed-off-by: Vijaya Kumar K
---
Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt
b
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm/include/uapi/asm/kvm.h | 7 ++
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
From: Vijaya Kumar K
In order to read or write to coproc regiter, the
access function is should allow the coproc_param to be non
constant.
Signed-off-by: Vijaya Kumar K
---
arch/arm/kvm/coproc.c | 20 ++--
arch/arm/kvm/coproc.h | 4 ++--
2 files changed, 12 insertions(+), 12 d
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
Use coproc_reg infrastructure to save and restore CPU
interface register of GICv3 for AArch32 host.
Signed-off-by: Vijaya Kumar K
---
arch/arm/kvm/Makefile | 2 +
virt/kvm/arm/vgic/vgic-coproc-reg-v3.c | 155 +
2 files cha
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The VM that supports SEIs expect it on destin
From: Vijaya Kumar K
To access CPU interface access in AArch32 mode, we need to
perform coproc_reg table lookup. For this introduce
find_coproc_reg_by_id() and export.
Also use this function internally in coproc.c wherever
required.
Signed-off-by: Vijaya Kumar K
---
arch/arm/kvm/coproc.c | 22
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
Documentation/virtual/kvm/devices/arm-vgic-v3.txt
The patch 3 & 4 are picked from the Pavel's pr
On Sun, Nov 20, 2016 at 6:50 PM, Christoffer Dall
wrote:
> On Sat, Nov 19, 2016 at 12:18:53AM +0530, Vijay Kilari wrote:
>> On Thu, Nov 17, 2016 at 9:39 PM, Christoffer Dall
>> wrote:
>> > On Thu, Nov 17, 2016 at 09:25:59PM +0530, Vijay Kilari wrote:
>> >&
On Mon, Nov 21, 2016 at 3:49 PM, Christoffer Dall
wrote:
> On Fri, Nov 18, 2016 at 10:28:34PM +0530, Vijay Kilari wrote:
>> On Thu, Nov 17, 2016 at 9:39 PM, Christoffer Dall
>> wrote:
>> > On Thu, Nov 17, 2016 at 09:25:59PM +0530, Vijay Kilari wrote:
>> >&
On Thu, Nov 17, 2016 at 9:39 PM, Christoffer Dall
wrote:
> On Thu, Nov 17, 2016 at 09:25:59PM +0530, Vijay Kilari wrote:
>> On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
>> wrote:
>> > On Fri, Nov 04, 2016 at 04:43:32PM +0530, vijay.kil...@gmail.com wrote:
&g
On Thu, Nov 17, 2016 at 9:39 PM, Christoffer Dall
wrote:
> On Thu, Nov 17, 2016 at 09:25:59PM +0530, Vijay Kilari wrote:
>> On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
>> wrote:
>> > On Fri, Nov 04, 2016 at 04:43:32PM +0530, vijay.kil...@gmail.com wrote:
&g
On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
wrote:
> On Fri, Nov 04, 2016 at 04:43:32PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The
On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
wrote:
> On Fri, Nov 04, 2016 at 04:43:31PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
>> and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
>> va
On Thu, Nov 17, 2016 at 12:22 AM, Christoffer Dall
wrote:
> On Fri, Nov 04, 2016 at 04:43:27PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> Read and write of some registers like ISPENDR and ICPENDR
>> from userspace requires special handling when compared to
>> guest access
On Wed, Nov 16, 2016 at 5:17 PM, Christoffer Dall
wrote:
> On Fri, Nov 04, 2016 at 04:43:26PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> This patchset adds API for saving and restoring
>> of VGICv3 registers to support live migration with new vgic feature.
>> This API defi
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 50
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
The patch 3 & 4 are
Hi Marc, Christoffer,
Do you have any review comments on this patch set?.
Regards
Vijay
On Fri, Sep 23, 2016 at 9:14 PM, wrote:
> From: Vijaya Kumar K
>
> This patchset adds API for saving and restoring
> of VGICv3 registers to support live migration with new vgic feature.
> This API defini
On Fri, Sep 23, 2016 at 9:14 PM, wrote:
> From: Vijaya Kumar K
>
> VGICv3 CPU interface registers are accessed using
> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> as 64-bit. The cpu MPIDR value is passed along with register id.
> is used to identify the cpu for registers a
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 50
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
The patch 3 & 4 are
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
On Thu, Sep 22, 2016 at 5:38 PM, Marc Zyngier wrote:
> On 20/09/16 07:12, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> Read and write of some registers like ISPENDR and ICPENDR
>> from userspace requires special handling when compared to
>> guest access for these registers.
>>
>> R
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
Compatible live migr
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 50
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
Hi Marc , Peter
On Sat, Sep 17, 2016 at 5:07 PM, Marc Zyngier wrote:
> On Sat, 17 Sep 2016 11:58:48 +0530
> Vijay Kilari wrote:
>
>> On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
>> > On 16/09/16 17:57, Vijay Kilari wrote:
>> >> On Fri, S
Hi Marc,
On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
> On 16/09/16 17:57, Vijay Kilari wrote:
>> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
>>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
>>>> From: Vijaya Kumar K
>>>>
>&g
On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
> On 16/09/16 17:57, Vijay Kilari wrote:
>> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
>>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
>>>> From: Vijaya Kumar K
>>>>
>>>
On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The cpu MPIDR value is passed a
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 50
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
ICH_VMCR_CTLR_MASK is changed to mask only ICC_CTLR_EL1 fields.
Also refactor vg
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
Compatible live migr
On Mon, Sep 12, 2016 at 6:45 PM, Marc Zyngier wrote:
> On 10/09/16 13:22, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> This patchset adds API for saving and restoring
>> of VGICv3 registers to support live migration with new vgic feature.
>> This API definition is as per version of
()
On Sun, Sep 11, 2016 at 1:26 PM, Marc Zyngier wrote:
> On Sat, 10 Sep 2016 17:52:17 +0530
> vijay.kil...@gmail.com wrote:
>
>> From: Vijaya Kumar K
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The cpu
On Mon, Sep 12, 2016 at 1:55 PM, Marc Zyngier wrote:
> On 10/09/16 13:22, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> +
>> +void vgic_uaccess_write_pending(struct kvm_vcpu *vcpu,
>> + gpa_t addr, unsigned int len,
>> + unsign
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 48
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
Compatible live migr
On Wed, Sep 7, 2016 at 12:49 AM, Christoffer Dall
wrote:
> On Tue, Sep 06, 2016 at 07:43:23PM +0530, Vijay Kilari wrote:
>> Resending in plain text mode
>>
>> On Tue, Sep 6, 2016 at 7:18 PM, Vijay Kilari wrote:
>> >
>> >
>> > On Tue, Aug 3
Resending in plain text mode
On Tue, Sep 6, 2016 at 7:17 PM, Vijay Kilari wrote:
>
>
> On Tue, Aug 30, 2016 at 6:01 PM, Christoffer Dall
> wrote:
>>
>> On Wed, Aug 24, 2016 at 04:50:06PM +0530, vijay.kil...@gmail.com wrote:
>> > From: Vijaya Kumar K
Resending in plain text mode
On Tue, Sep 6, 2016 at 7:18 PM, Vijay Kilari wrote:
>
>
> On Tue, Aug 30, 2016 at 7:15 PM, Christoffer Dall
> wrote:
>>
>> On Wed, Aug 24, 2016 at 04:50:08PM +0530, vijay.kil...@gmail.com wrote:
>> > From: Vijaya Kumar K
>
>
On Tue, Aug 30, 2016 at 7:30 PM, Christoffer Dall
wrote:
>
> On Wed, Aug 24, 2016 at 04:50:09PM +0530, vijay.kil...@gmail.com wrote:
> > From: Vijaya Kumar K
> > }
> > diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c
> > b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> > index 61abea0..fde1472 100644
> > ---
On Tue, Aug 30, 2016 at 7:15 PM, Christoffer Dall <
christoffer.d...@linaro.org> wrote:
> On Wed, Aug 24, 2016 at 04:50:08PM +0530, vijay.kil...@gmail.com wrote:
> > From: Vijaya Kumar K
>
> > diff --git a/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> > new file
On Tue, Aug 30, 2016 at 6:01 PM, Christoffer Dall <
christoffer.d...@linaro.org> wrote:
> On Wed, Aug 24, 2016 at 04:50:06PM +0530, vijay.kil...@gmail.com wrote:
> > From: Vijaya Kumar K
> >
> > VGICv3 Distributor and Redistributor registers are accessed using
> > KVM_DEV_ARM_VGIC_GRP_DIST_REGS a
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