ath according to the
specification.
Signed-off-by: Wei Huang
---
virt/kvm/arm/arch_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 3417f2dbc366..d43308dc3617 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/
On 03/30/2017 05:51 AM, Marc Zyngier wrote:
> On 29/03/17 19:56, Christoffer Dall wrote:
>> On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
>>> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
Hi Radha,
On Tue, Mar 28, 2017 at 12:58:24PM -0700, Radha Mohan wro
On 12/08/2016 11:05 AM, Andrew Jones wrote:
> The TCG PMU is barely implemented for ARM and not at all implemented
> for AArch64. Let's not bother running the TCG-only tests yet. We'll
> likely move them to a new TCG-only unittests.cfg at some point before
> re-enabling them too.
>
> Signed-off-
Reviewed-by: Wei Huang . I also tested on real machine
and it was working.
Thanks,
-Wei
On 12/08/2016 11:05 AM, Andrew Jones wrote:
> The spec for ID_DFR0_EL1 says "In an AArch64-only implementation,
> this register is UNKNOWN." Indeed ThunderX just returns zero when
> th
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/pmu.c | 66
. get_mpidr() is re-written with new macros.
Suggested-by: Andrew Jones
Signed-off-by: Wei Huang
---
lib/arm/asm/processor.h | 6 +++---
lib/arm/asm/sysreg.h | 19 +++
lib/arm64/asm/processor.h | 11 ---
lib/arm64/asm/sysreg.h| 26
To prepare for future support of ARMv8 system register, rename cp15.h file
to sysreg.h, with _ASMARM_CP15_H_ renamed to _ASMARM_SYSREG_H_ in header
file.
Signed-off-by: Wei Huang
---
arm/cstart.S | 2 +-
lib/arm/asm/{cp15.h => sysreg.h} | 6 +++---
2 files changed
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/Makefile.common | 3 +-
arm/pmu.c | 93
anks,
-Wei
Christopher Covington (3):
arm: Add PMU test
arm: pmu: Check cycle count increases
arm: pmu: Add CPI checking
Wei Huang (2):
arm: rename cp15.h to sysreg.h
arm: Add support for read_sysreg() and write_sysreg()
arm/Makefile.common | 3 +-
ar
On 12/01/2016 02:27 PM, Andre Przywara wrote:
> Hi,
>
> On 01/12/16 05:16, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Calculate the numbers of cycles per instruction (CPI) implied by ARM
>> PMU cycle counter values. The code includes a strict chec
On 12/01/2016 03:18 AM, Andrew Jones wrote:
> On Wed, Nov 30, 2016 at 11:16:41PM -0600, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
>> even for the smallest delta of two subsequent
On 12/01/2016 05:27 AM, Andre Przywara wrote:
> Hi,
>
> On 01/12/16 05:16, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
>> even for the smallest delta of two subsequent reads.
>>
On 12/01/2016 02:59 AM, Andrew Jones wrote:
>
> Should this be From: Andre?
>
> On Wed, Nov 30, 2016 at 11:16:39PM -0600, Wei Huang wrote:
>> This patch defines four macros to assist creating system register
>> accessors under both ARMv7 and AArch64:
>>
On 11/25/2016 08:26 AM, Andrew Jones wrote:
> On Fri, Nov 25, 2016 at 12:32:24PM +, Andre Przywara wrote:
>> Hi Drew,
>>
>>
>>
>> On 23/11/16 17:15, Andrew Jones wrote:
> +
> +#if defined(__arm__)
I guess you should use the arch specific header files we have in place
>>
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
arm/pmu.c | 94
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
correctly under
KVM mode.
https://lists.cs.columbia.edu/pipermail/kvmarm/2016-November/022134.html.
Thanks,
-Wei
Christopher Covington (3):
arm: Add PMU test
arm: pmu: Check cycle count increases
arm: pmu: Add CPI checking
Wei Huang (1):
arm: Define macros for accessing system registers
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU). PMU register
was read using the newly defined macros.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
with consistent naming,
get_##name() and set_##name(), which can be used by C code directly.
Signed-off-by: Andre Przywara
Signed-off-by: Wei Huang
---
lib/arm/asm/processor.h | 37 -
lib/arm64/asm/processor.h | 35 ---
2
On 11/30/2016 07:37 AM, Marc Zyngier wrote:
> On 30/11/16 11:48, Marc Zyngier wrote:
>> + Shannon
>>
>> On 29/11/16 22:04, Itaru Kitayama wrote:
>>> Hi,
>>>
>>> In a VM (virsh controlled, KVM acceleration enabled) on a recent
>>> kvmarm kernel host, I find I am unable to use perf to obtain
>>> pe
On 11/23/2016 11:15 AM, Andrew Jones wrote:
> On Wed, Nov 23, 2016 at 01:16:08PM +, Andre Przywara wrote:
>> Hi,
>>
>> On 22/11/16 18:29, Wei Huang wrote:
>>> From: Christopher Covington
>>>
>>> Beginning with a simple sanity check of the c
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
arm/pmu.c | 156
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/Makefile.common | 3 ++-
arm/pmu.c | 73
Changes from v11:
* Use report_info() to report PMU HW related info (implementer, id code, ...)
* Print PMU PMCR info in the same line
Note:
1) Current KVM code has bugs in handling PMCCFILTR write. A fix (see
below) is required for this unit testing code to work correctly under
KVM mode.
https://
On 11/23/2016 07:16 AM, Andre Przywara wrote:
> Hi,
>
> On 22/11/16 18:29, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Beginning with a simple sanity check of the control register, add
>> a unit test for the ARM Performance Monitors Unit (PMU).
>
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
arm/Makefile.common | 3 ++-
arm/pmu.c
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
arm/pmu.c | 156
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
Changes from v10:
* Change the name of loop test function to precise_instrs_loop()
* Minor comment fixes to measure_instrs() and to explain isb() in loop funcs
Note:
1) Current KVM code has bugs in handling PMCCFILTR write. A fix (see
below) is required for this unit testing code to work correctl
On 11/21/2016 03:40 PM, Christopher Covington wrote:
> Hi Wei,
>
> On 11/21/2016 03:24 PM, Wei Huang wrote:
>> From: Christopher Covington
>
> I really appreciate your work on these patches. If for any or all of these
> you have more lines added/modified than me (o
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
arm/Makefile.common | 3 ++-
arm/pmu.c
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/pmu.c | 156
Changes from v9:
* Move PMCCNTR related configuration from pmu_init() to sub-tests
* Change the name of loop test function to precise_cycles_loop()
* Print out error detail for each test case in check_cpi()
* Fix cpi convertion from argv
* Change the loop calculation in measure_instrs() after cpi i
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/pmu.c | 156
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
arm/Makefile.common | 3 ++-
arm/pmu.c
.
Thanks,
-Wei
Wei Huang (3):
arm: Add PMU test
arm: pmu: Check cycle count increases
arm: pmu: Add CPI checking
arm/Makefile.common | 3 +-
arm/pmu.c | 339
arm/unittests.cfg | 19 +++
3 files changed, 360 insertions(+), 1
On 11/16/2016 04:02 PM, Christopher Covington wrote:
> On 11/16/2016 12:46 PM, Marc Zyngier wrote:
>> On 16/11/16 14:38, Andrew Jones wrote:
>>> ARMv7-A isn't exactly the same as ARMv8-A32 (AArch32). This
>>> function allows unit tests to make the distinction.
>>
>> Hi Drew,
>>
>> Overall, having
(i.e. 0x11).
To support this patch and to prevent duplicated definitions, a limited
set of ARMv8 perf event types were relocated from perf_event.c to
asm/perf_event.h.
Signed-off-by: Wei Huang
---
arch/arm64/include/asm/perf_event.h | 10 +-
arch/arm64/kernel/perf_event.c | 10 +
On 11/14/2016 09:12 AM, Christopher Covington wrote:
> Hi Drew, Wei,
>
> On 11/14/2016 05:05 AM, Andrew Jones wrote:
>> On Fri, Nov 11, 2016 at 01:55:49PM -0600, Wei Huang wrote:
>>>
>>>
>>> On 11/11/2016 01:43 AM, Andrew Jones wrote:
>>>&g
On 11/11/2016 01:43 AM, Andrew Jones wrote:
> On Tue, Nov 08, 2016 at 12:17:14PM -0600, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
>> even for the smallest delta of two subsequent
On 11/11/2016 02:08 AM, Andrew Jones wrote:
> On Tue, Nov 08, 2016 at 12:17:15PM -0600, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Calculate the numbers of cycles per instruction (CPI) implied by ARM
>> PMU cycle counter values. The code includes
On 11/10/2016 11:17 AM, Will Deacon wrote:
> On Thu, Nov 10, 2016 at 03:32:12PM +, Marc Zyngier wrote:
>> On 10/11/16 15:12, Wei Huang wrote:
>>>
>>>
>>> On 11/10/2016 03:10 AM, Marc Zyngier wrote:
>>>> Hi Wei,
>>>>
>>&
On 11/10/2016 03:10 AM, Marc Zyngier wrote:
> Hi Wei,
>
> On 09/11/16 19:57, Wei Huang wrote:
>> This patch moves ARMv8-related perf event definitions from perf_event.c
>> to asm/perf_event.h; so KVM code can use them directly. This also help
>> remove a duplicat
This patch moves ARMv8-related perf event definitions from perf_event.c
to asm/perf_event.h; so KVM code can use them directly. This also help
remove a duplicated definition of SW_INCR in perf_event.h.
Signed-off-by: Wei Huang
---
arch/arm64/include/asm/perf_event.h | 161
.e. 0x11).
Signed-off-by: Wei Huang
---
virt/kvm/arm/pmu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 6e9c40e..69ccce3 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -305,7 +305,7 @@ void kvm_pmu_software_
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/pmu.c | 98
this unit testing code to work correctly under
KVM mode.
https://lists.cs.columbia.edu/pipermail/kvmarm/2016-November/022134.html.
2) Because the code was changed, Drew's original reviewed-by needs to
be acknowledged by him again.
-Wei
Wei Huang (3):
arm: Add PMU test
arm: pmu: Check cycle
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/Makefile.common | 3 ++-
arm/pmu.c | 73
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
On 11/02/2016 11:11 PM, c...@codeaurora.org wrote:
> Hi Wei,
>
> On 2016-11-02 14:55, Wei Huang wrote:
>> KVM calls kvm_pmu_set_counter_event_type() when PMCCFILTR is configured.
>> But this function can't deals with PMCCFILTR correctly because the
>> evtCou
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
---
arm/Makefile.common | 3 +-
arm/pmu.c | 82 +
arm/unittests.cfg | 2
Changes from v6:
* Add a new pmu testing for KVM mode in config file
* Add additional init code, including setting PMCNTENSET and PMCCFILTR,
before reading PMCCNTR. ARMv7 support is also provided
* Add cycle counter init code for CPI testing
* Fix pmu_data compilation issue (for gcc 4.8.5)
* Com
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values.
Signed-off-by: Christopher Covington
---
arm/pmu.c | 109 +-
1 file changed, 108 insertions(+), 1 deletion(-)
diff --git a/arm/pmu.c b/arm/p
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/pmu.c | 100 ++
1 file changed, 100
pu cycle" event type).
Signed-off-by: Wei Huang
---
virt/kvm/arm/pmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 6e9c40e..13cc812 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -379,7 +379,8 @@ void kvm_p
On 02/11/2016 09:33 AM, Julien Grall wrote:
> Introduce a structure which are filled up by the arch timer driver and
> used by the virtual timer in KVM.
>
> The first member of this structure will be the timecounter. More members
> will be added later.
>
> This is also dropping arch_timer_get_t
On 02/11/2016 09:33 AM, Julien Grall wrote:
> Hello,
>
> This small series allows an ARM64 ACPI based platform to use KVM.
>
> Currently the KVM code has to parse the firmware table to get the necessary
> information to setup the virtual timer and virtual GIC.
>
> However the parsing of those
On 02/09/2016 02:49 PM, Christoffer Dall wrote:
> On Mon, Feb 08, 2016 at 04:47:27PM +, Julien Grall wrote:
>> For now, the firmware tables are parsed 2 times: once in the GIC
>> drivers, the other timer when initializing the vGIC. It means code
>> duplication and make more tedious to add the
On 2/8/16 10:39, Julien Grall wrote:
> Hi,
>
> On 08/02/16 09:59, Marc Zyngier wrote:
>> On 05/02/16 17:07, Wei Huang wrote:
>>> Wei Huang (7):
>>>KVM: GIC: Move GIC DT probing code to GICv2 and GICv3 files
>>>KVM: GIC: Add extra fields to st
On 2/8/16 03:59, Marc Zyngier wrote:
> Wei,
>
> On 05/02/16 17:07, Wei Huang wrote:
>> This patch set enables ACPI support for KVM GIC. Note that the patches
>> are in fact the V3 of previously submitted patches (search "Enable ACPI
>> support for KVM ARM&qu
This patch extracts the common code from the DT probe function. With
this patch the DT function only fills out the following info in *vgic.
- maint_irq (mapped)
- GICH resource
- GICV resource
Note that vgic->vctrl_base io-remapping is now moved to vgic_v2_probe().
Signed-off-by: Wei Hu
In preparation for ACPI probing, this patch extracts the DT-neutral
code into vgic_v3_probe(). DT function nows fills out the following
info in *vgic:
- maint_irq (mapped)
- GICv resources
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v3.c | 75
This patch implements ACPI probing for GICv3.
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v3.c | 64 --
1 file changed, 62 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic-v3.c b/virt/kvm/arm/vgic-v3.c
index 5eca58a..5bfb9cb 100644
This patch creates common functions for both GICv2 and GICv3. The
existing functions are renamed to new names specifically for DT.
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v2.c | 44 +++-
virt/kvm/arm/vgic-v3.c | 37
This patch implements ACPI probing for GICv2.
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v2.c | 68 ++
1 file changed, 68 insertions(+)
diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c
index b60e73a..7de2a1f 100644
--- a/virt/kvm
s
revision, the version number is reset to v1.
By following Marc's prior comments, the main design idea is to let DT or
ACPI code to fill out the "struct vgic_params" which are extended to
include all GIC related info.
[1] https://lkml.org/lkml/2016/2/1/658
Thanks,
-Wei
Wei Huang
This patch adds new fields in the struct vgic_params to store the
resource info (base and size) of GICH & GICV interfaces. These new
fields will be used by the DT and ACPI probing code later.
Signed-off-by: Wei Huang
---
include/kvm/arm_vgic.h | 8 +++-
virt/kvm/arm/vgic-v2-em
This patch moves GIC DT probing code from vgic.c to GICv2 & GICv3
sub-files. The probing will start from GICv2. If the probing fails,
KVM will try to probe GICv3 then.
Signed-off-by: Wei Huang
---
include/kvm/arm_vgic.h | 6 ++
virt/kvm/arm/vgic-v2.c | 17 ++---
virt/kvm
On 10/18/2015 02:53 PM, Christoffer Dall wrote:
> On Sun, Oct 18, 2015 at 01:34:42PM +0530, Amit wrote:
>> From: Amit Singh Tomar
>>
>> This patch adds guest exit statistics to debugfs, This can be helpful
>> while measuring KVM performance.
>>
>> Signed-off-by: Amit Singh Tomar
>> ---
>> arch
On 09/24/2015 05:31 PM, Shannon Zhao wrote:
> Signed-off-by: Shannon Zhao
Missing commit message here.
> ---
> arch/arm64/kvm/reset.c | 3 +++
> include/kvm/arm_pmu.h | 2 ++
> virt/kvm/arm/pmu.c | 18 ++
> 3 files changed, 23 insertions(+)
>
> diff --git a/arch/arm64/
On 09/24/2015 05:31 PM, Shannon Zhao wrote:
> Add access handler which emulates writing and reading PMSWINC
> register and add support for creating software increment event.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 18 +-
> include/kvm/arm_pmu.h |
On 09/24/2015 05:31 PM, Shannon Zhao wrote:
> Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its
> reset handler. Add a new case to emulate reading to PMCCNTR register.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 17 +++--
> 1 file change
On 09/24/2015 05:31 PM, Shannon Zhao wrote:
> When we use tools like perf on host, perf passes the event type and the
> id of this event type category to kernel, then kernel will map them to
> hardware event number and write this number to PMU PMEVTYPER_EL0
> register. When getting the event numb
On 09/24/2015 05:31 PM, Shannon Zhao wrote:
> Add reset handler which gets host value of PMCR_EL0 and make writable
> bits architecturally UNKNOWN. Add a common access handler for PMU
> registers which emulates writing and reading register and add emulation
> for PMCR.
>
> Signed-off-by: Shannon
On 09/24/2015 05:31 PM, Shannon Zhao wrote:
> This patchset adds guest PMU support for KVM on ARM64. It takes
> trap-and-emulate approach. When guest wants to monitor one event, it
> will be trapped by KVM and KVM will call perf_event API to create a perf
> event and call relevant perf_event APIs
vhost drivers provide guest VMs with better I/O performance and lower
CPU utilization. This patch allows users to select vhost devices under
KVM configuration menu on ARM. This makes vhost support on arm/arm64
on a par with other architectures (e.g. x86, ppc).
Signed-off-by: Wei Huang
---
arch
out_free_context;
>
> #ifndef CONFIG_HOTPLUG_CPU
> free_boot_hyp_pgd();
>
kvm_host_cpu_state was allocated before kvm_timer_hyp_init() is called.
So it needs to be freed when kvm_timer_hyp_init() fails.
Reviewed-by: Wei Huang
Thanks,
-Wei
___
On 10/02/2015 10:48 AM, Christopher Covington wrote:
> Add test the ARM Performance Monitors Unit (PMU). The informational
> fields from the control register are printed, but not checked, and
> the number of cycles it takes to run a known-instruction-count loop
> is printed, but not checked. Once
On 09/16/2015 08:32 PM, Shannon Zhao wrote:
> Hi Wei,
>
> On 2015/9/17 5:07, Wei Huang wrote:
>> I am testing this series.
> Thanks for your time and help.
>
>> The first question is: do you plan to add ACPI
>> support in QEMU?
I saw "KVM_{SET/GET}_DEVIC
On 09/11/2015 03:54 AM, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This patchset adds guest PMU support for KVM on ARM64. It takes
> trap-and-emulate approach. When guest wants to monitor one event, it
> will be trapped by KVM and KVM will call perf_event API to create a perf
> event and call
On 06/10/2015 11:43 AM, Marc Zyngier wrote:
> On 10/06/15 05:16, Wei Huang wrote:
>> There are two GICs (GICv2 and GICv3) supported by KVM. So it is necessary
>> to find out GIC version before calling ACPI probing functions defined
>> in vgic-v2.c and vgic-v3.c.
>>
This patches enables ACPI support for KVM virtual arch timer. It allows
KVM to parse ACPI table for arch timer PPI when DT table is not present.
Signed-off-by: Alexander Spyridaki
Signed-off-by: Wei Huang
---
virt/kvm/arm/arch_timer.c | 75 +++
1
This patches enables ACPI support for KVM virtual GICv3. KVM parses
ACPI table for virt GIC related information and initializes resources.
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v3.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff
This patches enables ACPI support for KVM virtual GICv2. KVM parses
ACPI table for virt GIC related information and initializes resources.
Signed-off-by: Alexander Spyridaki
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v2.c | 50 +-
1 file
Verified patches on APM Mustang machine, which has arch_timer & GICv2
V1:
* Initial patchset
Wei Huang (5):
kvm: arm64: Enable ACPI support for virt arch timer
kvm: arm64: Dispatch virt GIC probing to device tree and ACPI
kvm: arm64: Detect GIC version for proper ACPI vGIC probing
k
of ACPI 5.1,
we use manual hardware discovery to find out GIC version.
NOTE: This patch is based on a recent patch by Hanjun Guo.
Signed-off-by: Hanjun Guo
Signed-off-by: Wei Huang
---
include/kvm/arm_vgic.h | 18 +
virt/kvm/arm/vgic-v2.c | 10 +
virt/kvm/arm/vgic-v3.c | 10
This patch creates a dispatch function to support virt GIC probing
in both device tree (DT) and ACPI environment. kvm_vgic_hyp_init()
will probe DT first. If failed, it will try ACPI.
Signed-off-by: Wei Huang
---
include/kvm/arm_vgic.h | 18 +-
virt/kvm/arm/vgic-v2.c | 8
Hi Christoffer and Marc,
Ping. Any comments on this patchset for V2?
Thanks,
-Wei
On 5/28/15 00:23, Wei Huang wrote:
Initial ACPI support for ARM64 has been accepted into Linux kernel recently.
Now it is a good time to re-visit ACPI support for KVM. This patchset
enables ACPI for both
On 05/29/2015 09:06 AM, Andrew Jones wrote:
> On Thu, May 28, 2015 at 01:34:33AM -0400, Wei Huang wrote:
>> This patches enables ACPI support for KVM virtual GICv2. KVM parses
>> ACPI table for virt GIC related information and initializes resources.
>>
>> Signed-
This patches enables ACPI support for KVM virtual GICv3. KVM parses
ACPI table for virt GIC related information and initializes resources.
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v3.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff
This patches enables ACPI support for KVM virtual arch timer. It allows
KVM to parse ACPI table for arch timer PPI when DT table is not present.
Signed-off-by: Alexander Spyridaki
Signed-off-by: Wei Huang
---
virt/kvm/arm/arch_timer.c | 64 +--
1
This patches enables ACPI support for KVM virtual GICv2. KVM parses
ACPI table for virt GIC related information and initializes resources.
Signed-off-by: Alexander Spyridaki
Signed-off-by: Wei Huang
---
virt/kvm/arm/vgic-v2.c | 49 -
1 file
of ACPI 5.1,
we use manual hardware discovery to find out GIC version.
NOTE: This patch is based on a recent patch by Hanjun Guo.
Signed-off-by: Hanjun Guo
Signed-off-by: Wei Huang
---
include/kvm/arm_vgic.h | 18 +
virt/kvm/arm/vgic-v2.c | 10 +
virt/kvm/arm/vgic-v3.c | 10
This patch creates a dispatch function to support virt GIC probing
in both device tree (DT) and ACPI environment. kvm_vgic_hyp_init()
will probe DT first. If failed, it will try ACPI.
Signed-off-by: Wei Huang
---
include/kvm/arm_vgic.h | 18 +-
virt/kvm/arm/vgic-v2.c | 8
distributor (search "ACPICA: Introduce GIC version for arm based system").
This patchset can be applied cleanly on top of Linx 4.1-rc1.
Wei Huang (5):
kvm: arm64: Enable ACPI support for virt arch timer
kvm: arm64: Dispatch virt GIC probing to device tree and ACPI
kvm: arm64:
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