Hi James
On 2020/4/14 20:18, James Morse wrote:
> Hi Geng,
>
> On 11/04/2020 13:17, Dongjiu Geng wrote:
>> When the RAS Extension is implemented, b0b011000, 0b011100,
>> 0b011101, 0b00, and 0b01, are not used and reserved
>> to the DFSC[5:0] of ESR_ELx, but the code still checks these
>>
On 2019/5/13 17:44, Peter Maydell wrote:
> On Mon, 13 May 2019 at 07:32, Dongjiu Geng wrote:
>>
>> When user space do memory recovery, it will check whether KVM and
>> guest support the error recovery, only when both of them support,
>> user space will do the error recovery. This patch exports thi
Hi James,
> Hi Dongjiu Geng,
>
> On 11/10/2018 20:07, Dongjiu Geng wrote:
> > The commit 539aee0edb9f ("KVM: arm64: Share the parts of get/set
> > events useful to 32bit") shares the get/set events helper for arm64
> > and arm32,
>
> Oops. I evidently didn't test this bit. Looks like I just depe
Hi Suzuki
On 2018/10/10 1:22, Suzuki K Poulose wrote:
>
>
> On 08/10/18 13:34, Dongjiu Geng wrote:
>> The commit 539aee0edb9f ("KVM: arm64: Share the parts of
>> get/set events useful to 32bit") shares the get/set events
>> helper for arm64 and arm32, it is better also share the check
>> for vcp
Hi Suzuki,
On 2018/10/10 0:34, Suzuki K Poulose wrote:
> Hi,
>
> On 08/10/18 13:34, Dongjiu Geng wrote:
>> Rename kvm_arch_dev_ioctl_check_extension() to
>> kvm_arch_vm_ioctl_check_extension(), because it does
>> not have any relationship with device.
>>
>> Renaming this function can make code re
Hi christoffer/marc,
Could you review this simple patch to enable the 32 bit KVM vcpu event
supports? Because below user space patch depended on it. thanks
https://patchwork.kernel.org/patch/10617601/
> subject: [PATCH 2/2] arm/arm64: KVM: share the check for vcpu events
> capability
>
On 2018/8/20 19:15, Marc Zyngier wrote:
> I'd prefer you fix the documentation rather than the code, as this would
> pointlessly break existing code.
Ok, sure. I will, thanks a lot.
___
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.c
On 2018/7/19 17:10, Peter Maydell wrote:
>> The user space will firstly check the KVM_CAP_VCPU_EVENTS through
>> kvm_has_vcpu_events() to know whether KVM can support get/set vcpu events,
>> If KVM supports get/set vcpu events, it will check
>> KVM_CAP_ARM_SET_SERROR_ESR to know whether can set
Hi peter,
Thanks for the review.
On 2018/7/18 0:36, Peter Maydell wrote:
> On 13 July 2018 at 16:47, James Morse wrote:
>> From: Dongjiu Geng
>>
>> For the arm64 RAS Extension, user space can inject a virtual-SError
>> with specified ESR. So user space needs to know whether KVM support
>> to i
On 2018/7/18 0:33, Peter Maydell wrote:
> On 13 July 2018 at 16:47, James Morse wrote:
>> From: Dongjiu Geng
>>
>> For the migrating VMs, user space may need to know the exception
>> state. For example, in the machine A, KVM make an SError pending,
>> when migrate to B, KVM also needs to pend an
On 2018/7/13 23:47, James Morse wrote:
> arm64's new use of KVMs get_events/set_events API calls isn't just
> for RAS, it allows an SError that has been made pending by KVM as
> part of its device emulation to be migrated.
>
> Wire this up for 32bit too.
>
> We only need to read/write the HCR_
On 2018/7/13 23:47, James Morse wrote:
> The get/set events helpers do some work to check reserved
> and padding fields are zero. This is useful on 32bit too.
>
> Move this code into virt/kvm/arm/arm.c, and give the arch
> code some underscores.
>
> This is temporarily hidden behind __KVM_HAVE_VC
> >> diff --git a/Documentation/virtual/kvm/api.txt
> >> b/Documentation/virtual/kvm/api.txt
> >> index d10944e619d3..e3940f8715a5 100644
> >> --- a/Documentation/virtual/kvm/api.txt
> >> +++ b/Documentation/virtual/kvm/api.txt
> >> @@ -835,11 +835,13 @@ struct kvm_clock_data e
> >>
> >> Capabilit
Hi James,
On 2018/7/11 0:49, James Morse wrote:
> The get/set events helpers to do some work to check reserved
> and padding fields are zero. This is useful on 32bit too.
>
> Move this code into virt/kvm/arm/arm.c, and give the arch
> code some underscores.
>
> This is temporarily hidden behind
Hi, James,
[...]
> diff --git a/Documentation/virtual/kvm/api.txt
> b/Documentation/virtual/kvm/api.txt
> index d10944e619d3..e3940f8715a5 100644
> --- a/Documentation/virtual/kvm/api.txt
> +++ b/Documentation/virtual/kvm/api.txt
> @@ -835,11 +835,13 @@ struct kvm_clock_data {
>
> Capability:
Hi James,
On 2018/7/11 0:49, James Morse wrote:
> Hi guys,
>
> This is GengDongjiu's get/set events series[0], with additional plumbing for
> 32bit.
Thanks for the extension to support 32bits platform, it is great
>
> This series adds the get/set events API to KVM for arm/arm64 so that
> user-
Increase the priority of the recovery work by scheduling it on the
> system_highpri_wq, then try to bump the current task off this CPU so that
> the recover work starts immediately.
>
> Reported-by: Xie XiuQi
> Signed-off-by: James Morse
> Reviewed-by: Punit Agrawal
> Test
Increase the priority of the recovery work by scheduling it on the
> system_highpri_wq, then try to bump the current task off this CPU so that
> the recover work starts immediately.
>
> Reported-by: Xie XiuQi
> Signed-off-by: James Morse
> Reviewed-by: Punit Agrawal
> Test
James,
>
>> I do not know when it is merge-window. About the apply version, it does not
>> have limited.
>
> 'git fetch' Linus' tree and look at the tags. 'v4.16' lost its '-rc' suffixes,
> and there isn't a 'v4.17-rc1' yet, so we are still in the merge window.
>
> Linus sends a message to LKM
James,
Thanks for this mail.
On 2018/4/13 0:14, James Morse wrote:
> Hi gengdongjiu,
>
> On 12/04/18 06:00, gengdongjiu wrote:
>> 2018-02-16 1:55 GMT+08:00 James Morse :
>>> On 05/02/18 11:24, gengdongjiu wrote:
>>>>> Is the emulated SError
Hi James,
Thanks for the comments.
2018-04-10 22:15 GMT+08:00, James Morse :
> Hi Dongjiu Geng,
>
> On 09/04/18 22:36, Dongjiu Geng wrote:
>> This new IOCTL exports user-invisible states related to SError.
>> Together with appropriate user space changes, it can inject
>> SError with specified sy
HI James,
Thanks for the review.
2018-04-10 22:15 GMT+08:00, James Morse :
> Hi Dongjiu Geng,
>
> On 09/04/18 22:36, Dongjiu Geng wrote:
>> Before user space injects a SError, it needs to know whether it can
>> specify the guest Exception Syndrome, so KVM should tell user space
>> whether it ha
Hi James，
thanks for this mail.
On 2018/4/10 22:15, James Morse wrote:
> Hi Dongjiu Geng,
>
> On 09/04/18 22:36, Dongjiu Geng wrote:
>> 1. Detect whether KVM can set set guest SError syndrome
>> 2. Support to Set VSESR_EL2 and inject SError by user space.
>> 3. Support live migration to keep S
Dear James,
Thanks for this mail and sorry for my late response.
2018-02-16 1:55 GMT+08:00 James Morse :
> Hi gengdongjiu, liu jun
>
> On 05/02/18 11:24, gengdongjiu wrote:
[]
>>
>>> Is the emulated SError routed following the routing rules for HCR_EL2.{AMO,
Hi James,
Thanks for your time to review and give comments.
[...]
> > +
> > +8.14 KVM_CAP_ARM_SET_SERROR_ESR
> > +
> > +Architectures: arm, arm64
> > +
> > +This capability indicates that userspace can specify syndrome value
> > +reported to guest OS when guest takes a virtual SError interrupt
Hi James,
Thanks for your review and good suggestion.
>
> Hi Dongjiu Geng,
>
> On 03/03/18 16:09, Dongjiu Geng wrote:
> > RAS Extension provides VSESR_EL2 register to specify virtual SError
> > syndrome value, this patch adds a new IOCTL to export user-invisible
> > states related to SError e
Hi James,
>
> Hi Dongjiu Geng,
>
> On 03/03/18 16:09, Dongjiu Geng wrote:
> > Export one API to specify virtual SEI syndrome value for guest, and
> > add a helper to get the VSESR_EL2 value.
>
> This patch adds two helpers that nothing calls... its not big, please merge
> it with the patch tha
Hi James,
> Hi gengdongjiu,
>
> On 26/02/18 16:13, gengdongjiu wrote:
> > 2018-02-24 1:58 GMT+08:00 James Morse :
> >> On 22/02/18 18:02, Dongjiu Geng wrote:
> >>> The RAS SError Syndrome can be Implementation-Defined,
> >>> arm64_is_ras_serror(
Hi James,
Thank you very much for this mail and your time to review this patch.
Appreciate that.
I will check it and reply.
On 2018/3/16 4:37, James Morse wrote:
> Hi Dongjiu Geng,
>
> On 03/03/18 16:09, Dongjiu Geng wrote:
>> Export one API to specify virtual SEI syndrome value
>> for guest
Hi James,
sorry for my late response due to chines new year.
2018-02-16 1:55 GMT+08:00 James Morse :
> Hi gengdongjiu,
>
> On 12/02/18 10:19, gengdongjiu wrote:
>> On 2018/2/10 1:44, James Morse wrote:
>>> The point? We can't know what a CPU without the RAS
Hi James,
Thanks a lot for your review.
2018-02-24 1:58 GMT+08:00 James Morse :
> Hi Dongjiu Geng,
>
> On 22/02/18 18:02, Dongjiu Geng wrote:
>> The RAS SError Syndrome can be Implementation-Defined,
>> arm64_is_ras_serror() is used to judge whether it is RAS SError,
>> but arm64_is_ras_serror(
Hi James,
Thanks for the mail.
On 2018/2/10 1:44, James Morse wrote:
[...]
>
>> its ESR is 0, can not control the virtual SError's syndrom value, it does
>> not have
>> such registers to control that.
>
> My point was its more nuanced than this: the ARM-ARM's
> TakeVirtualSErrorException() pse
[...]
>
> > Yes, I know you are dong that. Your serial's patch will consider all above
> things, right?
>
> Assuming I got it right, yes. It currently makes the race Xie XiuQi spotted
> worse,
> which I want to fix too. (details on the cover letter)
Ok.
>
>
> > If your patch can be consider
James,
Thank you for your time to reply me.
On 2018/1/31 3:21, James Morse wrote:
> Hi gengdongjiu,
>
> On 24/01/18 20:06, gengdongjiu wrote:
>>> On 06/01/18 16:02, Dongjiu Geng wrote:
>>>> The ARM64 RAS SError Interrupt(SEI) syndrome value is specific to the
>
On 2018/1/24 3:05, James Morse wrote:
>> do you mean we do not enable "CONFIG_ARM64_RAS_EXTN" in the
>> defconfig for ARM's SOC until kernel-first RAS is supported?
> I've no idea if or when we will do kernel-first, when I bring it up, its so we
> don't build a hybrid model, and we consider how we
Hi James,
thanks for the review.
On 2018/1/24 3:07, James Morse wrote:
> Hi Dongjiu Geng,
>
> On 06/01/18 16:02, Dongjiu Geng wrote:
>> RAS Extension add a VSESR_EL2 register which can provide
>> the syndrome value reported to software on taking a virtual
>> SError interrupt exception. This pat
Hi James,
Thanks a lot for your review and comments.
>
> Hi Dongjiu Geng,
>
> On 06/01/18 16:02, Dongjiu Geng wrote:
> > The ARM64 RAS SError Interrupt(SEI) syndrome value is specific to the
> > guest and user space needs a way to tell KVM this value. So we add a
> > new ioctl. Before user sp
Hi James,
Thanks for this mail.
> Hi gengdongjiu,
>
> On 23/01/18 09:06, gengdongjiu wrote:
> > On 2018/1/23 3:32, James Morse wrote:
> >>> it seems this "CONFIG_ARM64_RAS_EXTN" is not enabled in the
> >>> "arch/arm64/configs/defconfig&q
sorry fix a typo.
On 2018/1/23 17:23, gengdongjiu wrote:
>> There are problems with doing this:
>>
>> Oct. 18, 2017, 10:26 a.m. James Morse wrote:
>> | How do SEA and SEI interact?
>> |
>> | As far as I can see they can both interrupt each other, which isn&#x
Hi James,
On 2018/1/23 3:39, James Morse wrote:
> Hi Dongjiu Geng,
>
> (versions of patches 1,2 and 4 have been queued by Catalin)
>
> (Nit 'ACPI / APEI:' is the normal subject prefix for ghes.c, this helps the
> maintainers know which patches they need to pay attention to when you are
> touchin
Hi James,
On 2018/1/23 3:32, James Morse wrote:
>> it seems this "CONFIG_ARM64_RAS_EXTN" is not enabled in the
>> "arch/arm64/configs/defconfig",
>> if not, I want to enable this config to enable RAS feature in the defconfig.
>> do you agree?
> Sure. This series doesn't do a lot on its own, it e
2018-01-15 16:33 GMT+08:00 Christoffer Dall :
> On Fri, Jan 12, 2018 at 06:05:23PM +, James Morse wrote:
>> On 15/12/17 03:30, gengdongjiu wrote:
>> > On 2017/12/7 14:37, gengdongjiu wrote:
>
> [...]
>
>>
>> (I recall someone saying migration is needed
2018-01-13 2:05 GMT+08:00 James Morse :
> Hi gengdongjiu,
>
> On 16/12/17 04:47, gengdongjiu wrote:
>> [...]
>>>
>>>> + case ESR_ELx_AET_UER: /* The error has not been propagated */
>>>> + /*
>>>> + * Usersp
Hi James,
Sorry for my late response due to out of office recently.
2018-01-13 2:05 GMT+08:00 James Morse :
> Hi gengdongjiu,
>
> On 15/12/17 03:30, gengdongjiu wrote:
>> On 2017/12/7 14:37, gengdongjiu wrote:
>>>> We need to tackle (1) and (3) separately. Fo
Hi James,
thanks very much for your mail and reply, I will check it ASAP. Due to
recently busy with other thing, so reply may be late.
On 2018/1/13 2:05, James Morse wrote:
> Hi gengdongjiu,
>
> On 16/12/17 04:47, gengdongjiu wrote:
>> [...]
>>>
>>>> +
Hi Christoffer
On 2018/1/15 16:33, Christoffer Dall wrote:
> On Fri, Jan 12, 2018 at 06:05:23PM +, James Morse wrote:
>> On 15/12/17 03:30, gengdongjiu wrote:
>>> On 2017/12/7 14:37, gengdongjiu wrote:
>
> [...]
>
>>
>> (I recall someone saying
Hi James,
On 2018/1/16 3:38, James Morse wrote:
> From: Xie XiuQi
>
> ARM's v8.2 Extentions add support for Reliability, Availability and
> Serviceability (RAS). On CPUs with these extensions system software
> can use additional barriers to isolate errors and determine if faults
> are pending. A
Hi james/all,
whether it is possible you can have a look at this series patches?
thanks very much in advance for your time.
发件人：耿东久
收件人：christoffer.dall,marc.zyngier,li...@armlinux.org.uk,Catalin
Marinas,rjw,bp,robert.moore,lv.zheng,James.Morse,cor...@lwn.net,Will.Deacon,linux-...@vger.
On 2017/12/16 12:08, gengdongjiu wrote:
> On 2017/12/15 23:50, James Morse wrote:
>> +case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
>> +/*
>> + * The CPU can't make progress. The exception may have
>>
[...]
>
>> + case ESR_ELx_AET_UER: /* The error has not been propagated */
>> + /*
>> + * Userspace only handle the guest SError Interrupt(SEI) if the
>> + * error has not been propagated
>> + */
>> + run->exit_reason = KVM_EXIT_E
On 2017/12/15 23:50, James Morse wrote:
> + case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
> + /*
> + * The CPU can't make progress. The exception may have
> + * been imprecise.
> + */
> + return true;
For Recoverable
Hi James,
On 2017/12/16 2:52, James Morse wrote:
>> signal, it will record the CPER and trigger a IRQ to notify guest, as shown
>> below:
>>
>> SIGBUS_MCEERR_AR trigger Synchronous External Abort.
>> SIGBUS_MCEERR_AO trigger GPIO IRQ.
>>
>> For the SIGBUS_MCEERR_AO and SIGBUS_MCEERR_AR, we have a
On 2017/12/15 23:50, James Morse wrote:
> +asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
> +{
> + nmi_enter();
How about firstly let APEI kernel driver to handle it by adding
patch[1]? if the handling is successful, do_serror() direct return;
Otherwise con
Hi James,
On 2017/12/7 14:37, gengdongjiu wrote:
>> We need to tackle (1) and (3) separately. For (3) we need some API that lets
>> Qemu _trigger_ an SError in the guest, with a specified ESR. But, we don't
>> have
>> a way of migrating pending SError yet... wh
Hi James,
On 2017/12/7 3:04, James Morse wrote:
> Hi gengdongjiu,
>
> On 06/12/17 10:26, gengdongjiu wrote:
>> On 2017/11/15 0:00, James Morse wrote:
>>>> + * error has not been propagated
>>>> + */
>>>> + run->
On 2017/11/15 0:00, James Morse wrote:
>> + * error has not been propagated
>> + */
>> +run->exit_reason = KVM_EXIT_EXCEPTION;
>> +run->ex.exception = ESR_ELx_EC_SERROR;
>> +run->ex.error_code = KVM_SEI_SEV_RECOVERABLE;
>> +re
On 2017/11/29 21:22, Christoffer Dall wrote:
>> table, but it already unmap by host APEI driver, then
>> generate stage2 data abort again, so this will lead to dead
>> loop.
> Why does it lead to a loop? If the host has marked a page as unusable,
> shouldn't the guest stage 1 page table be backed
Hi james,
On 2017/11/16 2:25, James Morse wrote:
> What about 32bit? The register names and sizes are different. User-space would
> need a separate implementation to drive this. This is easier for the kernel
> to do
I agree with you that using different register names and sizes, such as 32 bit.
F
Hi James,
Thanks a lot for the review.
On 2017/11/15 0:00, James Morse wrote:
> Hi Dongjiu Geng,
>
> On 10/11/17 19:54, Dongjiu Geng wrote:
>> If it is not RAS SError, directly inject virtual SError,
>> which will keep the old way. If it is RAS SError, firstly
>> let host ACPI module to handl
Hi James,
Thank you very much for your comments and review.
On 2017/11/15 0:00, James Morse wrote:
> Hi Dongjiu Geng,
>
> On 10/11/17 19:54, Dongjiu Geng wrote:
>> This series patches mainly do below things:
>>
>> 1. Trap RAS ERR* registers Accesses to EL2 from Non-secure EL1,
>>KVM will w
>
> (While VSESR_EL2 is 64bit[0], the value gets written into the ESR, which is
> 32bit, so I doubt the top 32bits can be used, currently they are all
> reserved.)
In fact the valid bits for vsesr_el2 is 25bit, which will set to ESR.ISS, bits
[24:0].
ESR.IL and ESR.EC are not set by vsesr_el2.
Hi james,
On 2017/11/15 0:03, James Morse wrote:
>> Hope this helps?
> Yes, I'll go looking for a way to expose VSESR_EL2 to user-space.
what is the purpose to expose VSESR_EL2?
do you mean set its value after migration?
May be we can use similar below Mechanism
https://www.spinics.net/lists/arm
On 2017/11/10 2:14, James Morse wrote:
> Hi guys,
>
> On 19/10/17 15:57, James Morse wrote:
>> Known issues:
> [...]
>> * KVM-Migration: VDISR_EL2 is exposed to userspace as DISR_EL1, but how
>> should
>>HCR_EL2.VSE or VSESR_EL2 be migrated when the guest has an SError pending
>> but
>>
On 2017/11/1 22:16, Mark Rutland wrote:
>> it will report Error.
> Alternatives cannot be nested. You need to define a cap like:
>
> ARM64_HAS_RAS_NOT_IESB
>
> ... which is set when ARM64_HAS_RAS_EXTN && !ARM64_HAS_IESB.
>
> Then you can do:
>
> alternative_if ARM64_HAS_RAS_NOT_IESB
>
>
> On 01/11/17 12:54, gengdongjiu wrote:
> > Hi Robin,
> >
> > On 2017/11/1 19:24, Robin Murphy wrote:
> >>> + esb
> >>> +alternative_else_nop_endif
> >>> +1:
> >>> + .endm
> >> Having a branch in here is prett
Hi Robin,
On 2017/11/1 19:24, Robin Murphy wrote:
>> +esb
>> +alternative_else_nop_endif
>> +1:
>> +.endm
> Having a branch in here is pretty horrible, and furthermore using label
> number 1 has a pretty high chance of subtly breaking code where this
> macro is inserted.
>
> Can we not so
On 2017/11/1 19:32, James Morse wrote:
>> RAS&IESB for firmware first support". In Huawei's platform, we do not
>> support IESB, so software needs to insert that.
> Surely you don't implement it because your CPU doesn't need it. Can
> unrecoverable errors really cross an exception without becoming
On 2017/10/29 9:12, Marc Zyngier wrote:
> I'm sorry, but I can't manage to parse this commit message. How about
> something like this?
>
> "kvm_vcpu_dabt_isextabt() tries to match a full fault syndrome, but
> calls kvm_vcpu_trap_get_fault_type() that only returns the fault class,
> thus reducin
On 2017/10/28 2:28, Marc Zyngier wrote:
>> kvm_vcpu_trap_get_fault_type() will clear the low two bits to zero. So
>> I use FSC_SEA_TTW represent "Synchronous external abort on translation
>> table walk"
> I understand that, and I certainly not keen on adding another "fault
> type" for this.
Ok,
>
> On Thu, Oct 26 2017 at 6:07:01 pm BST, Dongjiu Geng
> wrote:
> > For this matching, current code using the {I,D}FSC range to match
> > kvm_vcpu_trap_get_fault_type() return value, but
> > kvm_vcpu_trap_get_fault_type() only return the part {I,D}FSC instead
> > of whole, so fix this issue
>
James,
Thanks for the comment.
On 2017/10/26 1:42, James Morse wrote:
> Hi gengdongjiu,
>
> On 20/10/17 16:33, gengdongjiu wrote:
>> As we discuss below solution:
>> When guest happen SEA/SEI, KVM calls memory_failure() to send an
>> asynchronous SIGBUS
>> s
On 2017/10/19 22:58, James Morse wrote:
> +alternative_if ARM64_HAS_RAS_EXTN
> + // If we have the RAS extensions we can consume a pending error
> + // without an unmask-SError and isb.
> + esb
> + mrs_s x2, SYS_DISR_EL1
I do not think you can get the right value when esb produc
Hi James,
On 2017/10/23 23:26, James Morse wrote:
> If you're suggesting Qemu should set a default 'unknown' ESR for use when KVM
> doesn't know what to do, and SError is pretty much its only option:
>
> Why would Qemu set anything other than impdef:all-zeros?
>
> The only use would be to fake t
2017-10-19 22:58 GMT+08:00 James Morse :
> Prior to v8.2's RAS Extensions, the HCR_EL2.VSE 'virtual SError' feature
> generated an SError with an implementation defined ESR_EL1.ISS, because we
> had no mechanism to specify the ESR value.
>
> On Juno this generates an all-zero ESR, the most signific
CC James.
> > In the user space, we can check the si_code, if it is
> > "BUS_MCEERR_AR", we use SEA notification type for the guest; if it is
> > "BUS_MCEERR_AO", we use SEI notification type for the guest.
> > Because there are only two values for si_code("BUS_MCEERR_AR" and
> > BUS_MCEERR_AO)
> > In the user space, we can check the si_code, if it is "BUS_MCEERR_AR",
> > we use SEA notification type for the guest; if it is "BUS_MCEERR_AO", we
> > use SEI notification type for the guest.
> > Because there are only two values for si_code("BUS_MCEERR_AR" and
> > BUS_MCEERR_AO), in which c
Hi james,
Thanks for the mail and sorry for my late response.
2017-10-19 1:21 GMT+08:00, James Morse :
> Hi Dongjiu Geng,
>
> On 17/10/17 15:14, Dongjiu Geng wrote:
>> ARMv8.2 adds a new bit HCR_EL2.TEA which controls to
>> route synchronous external aborts to EL2, and adds a
>> trap control bi
On 2017/10/7 1:31, James Morse wrote:
> Hi gengdongjiu,
>
> On 27/09/17 12:07, gengdongjiu wrote:
>> On 2017/9/23 0:51, James Morse wrote:
>>> If this wasn't a firmware-first notification, then you're right KVM hands
>>> the
>>> guest an asy
Hi james,
thanks for the mail, and sorry for my late response.
On 2017/10/7 0:46, James Morse wrote:
>>> will give you an BUS_MCEERR_AO signal for any guest memory that is
>>> affected, and a BUS_MCEERR_AR if the guest directly accesses a page of
>>> affected memory.
>>>
>>> What Qemu/kvmtoo
Hi James,
Thanks for your mail. and very sorry for my late response.
>
> Hi gengdongjiu,
>
> On 15/10/17 17:09, gengdongjiu wrote:
> >> On 13/10/17 10:25, gengdongjiu wrote:
> >>> In my first version patch [2], It sets the virtual ESR in the KVM,
> >>
Hi James,
> Hi gengdongjiu,
>
> On 14/09/17 12:12, gengdongjiu wrote:
> > On 2017/9/8 0:31, James Morse wrote:
> >> KVM already handles external aborts from lower exception levels, no
> >> more work needs doing for TEA.
> > If it is firmware first sol
Hi Christoffer
On 2017/10/17 3:59, Christoffer Dall wrote:
> On Mon, Oct 16, 2017 at 04:10:01PM +0000, gengdongjiu wrote:
>> Hi Marc,
>>
>>>
>>> Please also update the 32bit code accordingly, as it looks broken too.
>>
>> I have updated the 32 bit
Hi Marc,
>
> Please also update the 32bit code accordingly, as it looks broken too.
I have updated the 32 bit code according, in my hand, there is no arm32 host
environment,
So there is no method to verify it in the arm32 host, only verify the patch in
the arm64 host.
Anyway I firstly send th
Hi James,
>
>> Today I added the support to do some minimal emulation for
>> RAS-Error-Record registers, thanks
>> for the good suggestion.
>
> Where can I find this patch?
> I'd like to repost it as part of the SError_rework/RAS/IESB series: this is
> one
> of the bits KVM needs but I didn't touc
> In fact I have below method for that, what do you think about that?
>
> 1. If there is no RAS, old method, directly inject virtual SError, not need
> to specify ESR, as shown in the [1]
> 2. If there is RAS, KVM set "the kvm_run" guest exit type value to let user
> space handle the SError abo
Hi James,
Thanks for your mail.
> Hi gengdongjiu,
>
> On 13/10/17 10:25, gengdongjiu wrote:
> > After checking this patch, I think my patch[1] already include this
> > logic(only a little difference).
>
> Your kvm_handle_guest_sei() is similar to where this series
Hi Marc,
On 2017/10/13 23:12, Marc Zyngier wrote:
> On 13/10/17 15:29, gengdongjiu wrote:
>> Hi Marc,
>> Thank you very much for your time to review it.
>>
>>> On 12/10/17 17:44, Dongjiu Geng wrote:
>>>> When a exception is trapped to EL2, hardware us
Hi Marc,
Thank you very much for your time to review it.
> On 12/10/17 17:44, Dongjiu Geng wrote:
> > When a exception is trapped to EL2, hardware uses ELR_ELx to hold the
> > current fault instruction address. If KVM wants to inject a abort to
> > 32 bit guest, it needs to set the LR registe
Hi James,
After checking this patch, I think my patch[1] already include this
logic(only a little difference). In my first version patch [2], It sets the
virtual ESR in the KVM, but Marc and
other people disagree that[3][4],and propose to set its value and injection by
userspace(when RAS is
>> What you may be seeing is some awkwardness with the change in the SError ESR
>> with v8.2. Previously the VSE mechanism injected an impdef SError, (but they
>> were all impdef so it didn't matter).
>> With VSESR_EL2 KVM has to specify one, and all-zeros is a bad choice as this
>> means 'classifi
Hi James,
Sorry for my late response, thank you very much for comments.
On 2017/9/23 0:51, James Morse wrote:
[.]
>>
>> CC Achin
>>
>> I have some personal opinion, if you think it is not right, hope you can
>> point out.
>>
>> Synchronous External Abort and SError Interrupt are hardware
Hi James,
Thank you for your reply.
On 2017/9/23 0:39, James Morse wrote:
> Hi gengdongjiu,
>
> On 18/09/17 14:36, gengdongjiu wrote:
>> On 2017/9/14 21:00, James Morse wrote:
>>> On 13/09/17 08:32, gengdongjiu wrote:
>>>> On 2017/9/8 0:30, James Morse wro
Hi James
On 2017/9/14 21:00, James Morse wrote:
> Hi gengdongjiu,
> user-space can choose whether to use SEA or SEI, it doesn't have to choose the
> same notification type that firmware used, which in turn doesn't have to be
> the
> same as that used by the CPU to
Hi, Christoffer
On 2017/9/19 6:32, Christoffer Dall wrote:
> Hi,
>
> On Mon, Sep 18, 2017 at 09:49:25PM +0800, gengdongjiu wrote:
>> To KVM mailing List about below question, thanks.
>>
>
> [Please send properly formatted and written e-mails to this mailing
> lis
To KVM mailing List about below question, thanks.
On 2017/9/18 21:17, Matt Evans wrote:
> Hi Gengdongjiu,
>
>
>> On 18 Sep 2017, at 07:39, gengdongjiu wrote:
>>
>> Hi Matt,
>> sorry to disturb you, I want to consult you a question about the function
>&g
James，
Thanks for your comments, hope we can make the solution better.
On 2017/9/14 21:00, James Morse wrote:
> Hi gengdongjiu,
>
> (re-ordered hunks)
>
> On 13/09/17 08:32, gengdongjiu wrote:
>> On 2017/9/8 0:30, James Morse wrote:
>>> On 28/08/17 11:3
On 2017/9/14 20:35, James Morse wrote:
>> James, whether it is possible you can review the previous v5 patch which
>> adds the support for
> Spreading 'current discussion' over two versions is a problem for anyone
> trying
> to follow this series.
>
> If you post a newer version its normal for
James,
On 2017/9/8 0:31, James Morse wrote:
> KVM already handles external aborts from lower exception levels, no more work
> needs doing for TEA.
If it is firmware first solution, that is SCR_EL3.EA=1, all SError interrupt
and synchronous External
Abort exceptions are taken to EL3, so EL3 firmwa
On 2017/9/13 18:52, Peter Maydell wrote:
> This question seems to be not really related to the review
> comment that it is responding to.
>
> (1) If the host does not support notifying us about
> errors, then there is clearly nothing to do in this
> code, because we will never get a notification
On 2017/9/8 0:31, James Morse wrote:
> Hi Dongjiu Geng,
>
> On 28/08/17 11:38, Dongjiu Geng wrote:
>> ARMv8.2 adds a new bit HCR_EL2.TEA which controls to
>> route synchronous external aborts to EL2, and adds a
>> trap control bit HCR_EL2.TERR which controls to
>> trap all Non-secure EL1&0 error
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