On 2020-06-09 08:48, Auger Eric wrote:
Hi Marc,
On 6/8/20 7:19 PM, Marc Zyngier wrote:
Hi Eric,
On 2020-06-08 17:58, Auger Eric wrote:
Hi Marc,
On 5/26/20 6:11 PM, Marc Zyngier wrote:
On a system that uses SPIs to implement MSIs (as it would be
the case on a GICv2 system exposing a GICv2m
Hi Marc,
On 6/8/20 7:19 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On 2020-06-08 17:58, Auger Eric wrote:
>> Hi Marc,
>>
>> On 5/26/20 6:11 PM, Marc Zyngier wrote:
>>> On a system that uses SPIs to implement MSIs (as it would be
>>> the case on a GICv2 system exposing a GICv2m to its guests),
>>> we
Hi Eric,
On 2020-06-08 17:58, Auger Eric wrote:
Hi Marc,
On 5/26/20 6:11 PM, Marc Zyngier wrote:
On a system that uses SPIs to implement MSIs (as it would be
the case on a GICv2 system exposing a GICv2m to its guests),
we deny the possibility of injecting SPIs on the in-atomic
fast-path.
Hi Marc,
On 5/26/20 6:11 PM, Marc Zyngier wrote:
> On a system that uses SPIs to implement MSIs (as it would be
> the case on a GICv2 system exposing a GICv2m to its guests),
> we deny the possibility of injecting SPIs on the in-atomic
> fast-path.
>
> This results in a very large amount of
Hi Marc,
On 2020/5/27 15:55, Marc Zyngier wrote:
Hi Zenghui,
On 2020-05-27 08:41, Zenghui Yu wrote:
On 2020/5/27 0:11, Marc Zyngier wrote:
On a system that uses SPIs to implement MSIs (as it would be
the case on a GICv2 system exposing a GICv2m to its guests),
we deny the possibility of
Hi Zenghui,
On 2020-05-27 08:41, Zenghui Yu wrote:
On 2020/5/27 0:11, Marc Zyngier wrote:
On a system that uses SPIs to implement MSIs (as it would be
the case on a GICv2 system exposing a GICv2m to its guests),
we deny the possibility of injecting SPIs on the in-atomic
fast-path.
This
On 2020/5/27 0:11, Marc Zyngier wrote:
On a system that uses SPIs to implement MSIs (as it would be
the case on a GICv2 system exposing a GICv2m to its guests),
we deny the possibility of injecting SPIs on the in-atomic
fast-path.
This results in a very large amount of context-switches
(roughly
On a system that uses SPIs to implement MSIs (as it would be
the case on a GICv2 system exposing a GICv2m to its guests),
we deny the possibility of injecting SPIs on the in-atomic
fast-path.
This results in a very large amount of context-switches
(roughly equivalent to twice the interrupt rate)