On Thu, 15 Jul 2021 12:51:49 +0100,
Robin Murphy wrote:
>
> On 2021-07-15 12:11, Marc Zyngier wrote:
> > Hi Alex,
> >
> > On Wed, 14 Jul 2021 16:48:07 +0100,
> > Alexandru Elisei wrote:
> >>
> >> Hi Marc,
> >>
> >> On 7/13/21 2:58 PM, Marc Zyngier wrote:
> >>> A number of the PMU sysregs
On 2021-07-15 12:11, Marc Zyngier wrote:
Hi Alex,
On Wed, 14 Jul 2021 16:48:07 +0100,
Alexandru Elisei wrote:
Hi Marc,
On 7/13/21 2:58 PM, Marc Zyngier wrote:
A number of the PMU sysregs expose reset values that are not in
compliant with the architecture (set bits in the RES0 ranges,
for
Hi Alex,
On Wed, 14 Jul 2021 16:48:07 +0100,
Alexandru Elisei wrote:
>
> Hi Marc,
>
> On 7/13/21 2:58 PM, Marc Zyngier wrote:
> > A number of the PMU sysregs expose reset values that are not in
> > compliant with the architecture (set bits in the RES0 ranges,
> > for example).
> >
> > This in
Hi Marc,
On 7/13/21 2:58 PM, Marc Zyngier wrote:
> A number of the PMU sysregs expose reset values that are not in
> compliant with the architecture (set bits in the RES0 ranges,
> for example).
>
> This in turn has the effect that we need to pointlessly mask
> some register when using them.
>
>
On Tue, Jul 13, 2021 at 04:59:58PM +0100, Marc Zyngier wrote:
> On Tue, 13 Jul 2021 15:39:49 +0100,
> "Russell King (Oracle)" wrote:
> >
> > On Tue, Jul 13, 2021 at 02:58:58PM +0100, Marc Zyngier wrote:
> > > +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct
> > > sys_reg_desc *r)
On Tue, 13 Jul 2021 15:39:49 +0100,
"Russell King (Oracle)" wrote:
>
> On Tue, Jul 13, 2021 at 02:58:58PM +0100, Marc Zyngier wrote:
> > +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc
> > *r)
> > +{
> > + u64 n, mask;
> > +
> > + /* No PMU available, any PMU reg
On Tue, Jul 13, 2021 at 02:58:58PM +0100, Marc Zyngier wrote:
> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc
> *r)
> +{
> + u64 n, mask;
> +
> + /* No PMU available, any PMU reg may UNDEF... */
> + if (!kvm_arm_support_pmu_v3())
> + return;
>
A number of the PMU sysregs expose reset values that are not in
compliant with the architecture (set bits in the RES0 ranges,
for example).
This in turn has the effect that we need to pointlessly mask
some register when using them.
Let's start by making sure we don't have illegal values in the
