On Fri, Jun 29, 2018 at 10:21:27AM +0100, Marc Zyngier wrote:
> On Fri, 29 Jun 2018 10:07:50 +0100,
> Christoffer Dall wrote:
> >
> > On Fri, Jun 29, 2018 at 09:09:47AM +0100, Marc Zyngier wrote:
> > > On Thu, 28 Jun 2018 21:56:38 +0100,
> > > Christoffer Dall wrote:
> > > >
> > > > On Wed, Jun
On Fri, 29 Jun 2018 10:07:50 +0100,
Christoffer Dall wrote:
>
> On Fri, Jun 29, 2018 at 09:09:47AM +0100, Marc Zyngier wrote:
> > On Thu, 28 Jun 2018 21:56:38 +0100,
> > Christoffer Dall wrote:
> > >
> > > On Wed, Jun 27, 2018 at 01:20:53PM +0100, Marc Zyngier wrote:
> > > > Up to ARMv8.3, the
On Fri, Jun 29, 2018 at 09:09:47AM +0100, Marc Zyngier wrote:
> On Thu, 28 Jun 2018 21:56:38 +0100,
> Christoffer Dall wrote:
> >
> > On Wed, Jun 27, 2018 at 01:20:53PM +0100, Marc Zyngier wrote:
> > > Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
> > > results in the strongest
On Thu, 28 Jun 2018 21:56:38 +0100,
Christoffer Dall wrote:
>
> On Wed, Jun 27, 2018 at 01:20:53PM +0100, Marc Zyngier wrote:
> > Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
> > results in the strongest attribute of the two stages. This means
> > that the hypervisor has to
On Wed, Jun 27, 2018 at 01:20:53PM +0100, Marc Zyngier wrote:
> Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
> results in the strongest attribute of the two stages. This means
> that the hypervisor has to perform quite a lot of cache maintenance
> just in case the guest has
On 27/06/18 17:20, Suzuki K Poulose wrote:
> Marc,
>
> On 27/06/18 13:20, Marc Zyngier wrote:
>> Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
>> results in the strongest attribute of the two stages. This means
>> that the hypervisor has to perform quite a lot of cache
Marc,
On 27/06/18 13:20, Marc Zyngier wrote:
Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
results in the strongest attribute of the two stages. This means
that the hypervisor has to perform quite a lot of cache maintenance
just in case the guest has some non-cacheable
Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
results in the strongest attribute of the two stages. This means
that the hypervisor has to perform quite a lot of cache maintenance
just in case the guest has some non-cacheable mappings around.
ARMv8.4 solves this problem by
