Re: [PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register

2015-12-15 Thread Marc Zyngier
On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which > is mapped to PMEVCNTRn. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses vcpu_sys_reg() to access their values to avoi

[PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register

2015-12-15 Thread Shannon Zhao
From: Shannon Zhao These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which is mapped to PMEVCNTRn. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big endian. When reading these regi