On Mon, Mar 10, 2014 at 10:44:05AM +, karim.allah.ah...@gmail.com wrote:
I have two questions:
1- I was wondering what should be the expected semantics of
flush_cache_all on a Big.LITTLE architecture.
I can see that the implementation of this function under linux kernel
is doing the
Hi Nico,
On 16 May 2013 19:21, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Thu, 16 May 2013, Liviu Dudau wrote:
From previous discussions between Achin, Charles and Nico I am aware
that Nico has decided for the moment that target residency should be
useful enough to be used by MCPM.
On Fri, Mar 01, 2013 at 08:41:47AM +, Anup Patel wrote:
This patch adds support for using earlyprintk with 8250/16550 UART
ports.
The 8250/16550 UART can either have 8-bit or 32-bit aligned registers
which is HW vendor dependent.
Kernel args for 8-bit aligned regs:
Hi Tixy,
On Wed, Jan 09, 2013 at 05:04:38PM +, Jon Medhurst (Tixy) wrote:
Patch 25c92a37a (arm64: Always select ARM_AMBA and GENERIC_GPIO)
expects platforms to have GPIO so we need to make sure vexpress
always has this by selecting ARCH_REQUIRE_GPIOLIB.
Without this change drivers like
On 16 February 2012 18:14, viresh kumar viresh.li...@gmail.com wrote:
On Thu, Feb 16, 2012 at 9:48 AM, Catalin Marinas
catalin.mari...@arm.com wrote:
The DMA API implementation on ARM takes care of the cache cleaning and
invalidating.
I believe that this is the reason why we have cache re
On Thu, Feb 16, 2012 at 04:41:02PM +, viresh kumar wrote:
Sorry for starting the long old thread again, but i have to start it as i
was a bit confused. :(
We know that we can't have multiple mappings with different attributes
to the same physical memory on ARMv6+ machines due to
On Thu, Feb 16, 2012 at 05:22:42PM +, Russell King - ARM Linux wrote:
On Thu, Feb 16, 2012 at 05:15:20PM +, Catalin Marinas wrote:
On Thu, Feb 16, 2012 at 04:41:02PM +, viresh kumar wrote:
Sorry for starting the long old thread again, but i have to start it as i
was a bit
On Thu, Feb 16, 2012 at 05:37:02PM +, viresh kumar wrote:
On Thu, Feb 16, 2012 at 9:15 AM, Catalin Marinas
catalin.mari...@arm.com wrote:
To summarise, if you mix Normal with Device or SO memory, you only get
the guarantees of the Normal memory (e.g. early write acknowledgement,
write
On Thu, Dec 01, 2011 at 03:42:19PM +, Arnd Bergmann wrote:
On Thursday 01 December 2011, Catalin Marinas wrote:
Given the way register banking is done on AArch64, issuing an HVC on a
32-bit guest OS doesn't require translation on a 64-bit hypervisor. We
have a similar implementation
On Thu, Dec 01, 2011 at 04:44:40PM +, Arnd Bergmann wrote:
On Thursday 01 December 2011, Catalin Marinas wrote:
On Thu, Dec 01, 2011 at 03:42:19PM +, Arnd Bergmann wrote:
On Thursday 01 December 2011, Catalin Marinas wrote:
How do you deal with signed integer arguments passed
On 30 November 2011 11:39, Stefano Stabellini
stefano.stabell...@eu.citrix.com wrote:
A git branch is available here (not ready for submission):
git://xenbits.xen.org/people/sstabellini/linux-pvhvm.git arm
the branch above is based on git://linux-arm.org/linux-2.6.git arm-lpae,
even though
On Tue, Jun 21, 2011 at 01:36:15PM -0700, Stephen Boyd wrote:
On 06/16/2011 11:54 PM, Vincent Guittot wrote:
On 16 June 2011 21:40, Stephen Boyd sb...@codeaurora.org wrote:
The ARM ARM says these fields are IMPLEMENTATION DEFINED meaning that
different vendors may attribute different
On 6 December 2010 17:35, Dave Martin dave.mar...@linaro.org wrote:
* Explicitly build a few parts of sleep34xx.S as ARM.
* lock_scratchpad_sem is kept as ARM because of the need to
synchronise with hardware (?) using the SWP instruction.
* save_secure_ram_context and
Hi Nicolas,
On Thu, 2010-11-11 at 17:38 +, Nicolas Pitre wrote:
On Thu, 11 Nov 2010, Lorenzo Pieralisi wrote:
To sum it up, I am just asking you what are your plans for the linaro-next
tree and the operating mode we should aim for.
I'm still wondering about that myself at the moment.
On Sat, 2010-10-16 at 18:21 +0100, Bobby Batacharia wrote:
Yes, the earlier the better to starting incorporating the
changes in Linux.
[...]
Our plan is definitely to get this into the Linaro kernel for the
11.05 release. My preferred approach is to get it into Catalin's
public tree by
On Sat, 2010-10-16 at 02:05 +0100, Woodruff, Richard wrote:
From: linaro-dev-boun...@lists.linaro.org [mailto:linaro-dev-
boun...@lists.linaro.org] On Behalf Of Peter Maydell
One of the Valgrind subtools is Cachegrind; this is a cache
profiler. (It simulates the I1, D1 and L2 caches so
On Thu, 2010-09-23 at 16:15 +0100, Arnd Bergmann wrote:
On Thursday 23 September 2010, Nicolas Pitre wrote:
This highmem topic comes from the fact that highmem will be needed in
the period of time between now and LPAE where we have boards with lots
of memory but we can't address it
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