On 11/06/2010 01:38 AM, Richard Earnshaw wrote:
On Wed, 2010-11-03 at 17:39 +0800, Yao Qi wrote:
Hi,
I am backporint some patches from FSF mainline, which may improve Linaro
4.5 gcc on thumb2 speed.
The first one is done by Richard E. "Improve optimization to transform
TST into LSLS"
http://gc
On Wed, 2010-11-03 at 17:39 +0800, Yao Qi wrote:
> Hi,
> I am backporint some patches from FSF mainline, which may improve Linaro
> 4.5 gcc on thumb2 speed.
>
> The first one is done by Richard E. "Improve optimization to transform
> TST into LSLS"
> http://gcc.gnu.org/ml/gcc-patches/2010-06/ms
Yao Qi wrote:
6801 ldr r1, [r0, #0]
f831 3013 ldrh.w r3, [r1, r3, lsl #1]
-f413 6f00 tst.w r3, #2048 ; 0x800
-f43f af41 beq.w cc
+0518 lsls r0, r3, #20
+f57f af44 bpl.w cc
4610 mov r0, r2
Someone suggests that the slowdown might be caused by usage of r0 in
first instruction. Since r0 is used
On 11/03/2010 05:39 PM, Yao Qi wrote:
Hi,
I am backporint some patches from FSF mainline, which may improve Linaro
4.5 gcc on thumb2 speed.
The first one is done by Richard E. "Improve optimization to transform
TST into LSLS"
http://gcc.gnu.org/ml/gcc-patches/2010-06/msg02518.html
After it appli
Hi,
I am backporint some patches from FSF mainline, which may improve Linaro
4.5 gcc on thumb2 speed.
The first one is done by Richard E. "Improve optimization to transform
TST into LSLS"
http://gcc.gnu.org/ml/gcc-patches/2010-06/msg02518.html
After it applied to Linaro 4.5 tree, EEMBC speed
