(someone wrote)
> Realize that MIPS actually means Misleading
> Indicator of Processor Speed.
(snip of clock rate comparison)
Clock rate is almost never useful for comparing between
different types of processors, or even different versions
of similar processors. There are many design tradeoffs
t
(snip about VM behavior when the console goes away)
> This behavior is not unique to VM at all -- it's exactly equivalent to
> hitting L1-A on a Sparc console and leaving it sitting at the "ok" PROM
> prompt -- you don't let people near your Sparc consoles if they don't
> know how to fix what the
> I found the solution to the problem I had with an Oracle 10g
> installation. By reading the full install manual for Oracle 10g for
> Linux x86-64, (several hundred pages, instead of the 20 or so pages for
> a quick install), I found that it seemed to need an entry in the
> /etc/hosts file.
> I
"McKown, John" <[EMAIL PROTECTED]> wrote:
(snip)
> VSAM does not use hardware keys. It is composed of fixed length "Control
> Intervals" which are composed of one or more fixed blocks on DASD. It
> could be considered "FBA compatable". There are a set of possible
> "Control Intervals" for a VSAM f
Dennis Musselwhite <[EMAIL PROTECTED]> wrote:
>From William P. Scully:
>> As you might expect, we at Computer Associates run more than one z/VM
>> node, and z/VM on more than one physical processor. We have embraced
>> using Virtual Switch technology for all the good reasons that Alan
>> Altmark
I asked on comp.dcon.lans.ethernet, and Rich Seifert,
a member of the ethernet standards group since just
about the beginning answered.
His answer: The very first sentence of clause 40 of
IEEE 802.3 states: "The 1000BASE-T PHY is one of the
Gigabit Ethernet family of high-speed CSMA/CD
network spe
Normally, you only need to worry about access due to
other CPU's or channels.
For an interruptible instruction, you also need to worry
about access by other tasks on the same CPU.
In the olden days, the interval timer at address 80 could
be updated with an MVC instruction. The new value was
stor
The 360/91 and maybe the 6600 were prominent in books
on pipelined architectures for many years.
The goal of the 360/91 was one instruction per clock cycle,
so not superscalar, but still a tough goal with slow core
memory. (16 way interleaved, but at over 10 times the
cycle time.)
A pipelined ex
I think this has been discussed in other lists, but not this
one. Because of the 4K key so-called feature, running VM/370
on a P/370 or P/390 in S/370 mode requires that CR0 bit 7
be set. Unfortunately, VM/370 doesn't normally do that.
VM/370 changes CR0 in many different places, and all those
m
> I hope i've sent this inquiry to the correct address.
> The other night our SUN system running Solaris 2.6 crashed.
> Attached via NFS mount were a couple of LINUX machines
> (each was running SLACKWARE 2.2.16). When the SUN box
> crashed it appears to have hosed the linux machines.
> We couldn
Ulrich Weigand <[EMAIL PROTECTED]> wrote:
> Dave Rivers wrote:
> >That is, of course one of the issues. The i386 IEEE implementation
> >is not the same as the mainframe, particularly when two variables
> >are loaded into registers and arithmetic is applied. The result
> >will be different.
There is discussion on another list about the ability to
run MVS software under L/390.
This would seem to me to be similar to what CMS does when running
MVS object or load modules. One requirement is to emulate
the system SVC's. Two things are needed: that Linux doesn't use the
required SVC's
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