On Oct 29, 2013, at 7:38 PM, Mark Rutland wrote:
On Tue, Oct 29, 2013 at 06:00:59PM +, Stephen Boyd wrote:
On 10/29/13 01:21, Kumar Gala wrote:
On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt
On Tuesday 29 October 2013, Daniel Walker wrote:
Why wouldn't you just update it to use the device tree ? There are lots
of phones our there using 7x30 ..
This is one that Qualcomm specifically upstreamed, so what was the point
of upstreaming it ?
Things like this happen a lot: you start
On Tuesday 29 October 2013, Daniel Walker wrote:
Isn't this the Nexus one platform ? Same as the last one , why don't you
just update it to use the device tree? This doesn't seem like it would
be all that difficult.
Please don't top-post.
On Mon, Oct 28, 2013 at 01:43:26PM -0700, David
On Wed, Oct 30, 2013 at 02:30:23PM +0100, Arnd Bergmann wrote:
On Tuesday 29 October 2013, Daniel Walker wrote:
Isn't this the Nexus one platform ? Same as the last one , why don't you
just update it to use the device tree? This doesn't seem like it would
be all that difficult.
Please
On 10/28, Josh Cartwright wrote:
+
+/**
+ * pa_write_data: write 1..4 bytes from buf to pmic-arb's register
+ * @bc byte-count -1. range: 0..3
+ * @reg register's address
+ * @buf buffer to write. length must be bc+1
Missing colon between variable and description.
+ */
+static void
On 10/28, Josh Cartwright wrote:
@@ -108,12 +111,17 @@ struct spmi_pmic_arb_dev {
void __iomem*base;
void __iomem*intr;
void __iomem*cnfg;
+ unsigned intirq;
boolallow_wakeup;
spinlock_t
Stephen-
Thanks for all the comments.
On Wed, Oct 30, 2013 at 11:17:55AM -0700, Stephen Boyd wrote:
On 10/28, Josh Cartwright wrote:
@@ -108,12 +111,17 @@ struct spmi_pmic_arb_dev {
void __iomem*base;
void __iomem*intr;
void __iomem*cnfg;
On Wed, Oct 30, 2013 at 11:05:36AM -0700, Stephen Boyd wrote:
On 10/28, Josh Cartwright wrote:
+
+/**
+ * pa_write_data: write 1..4 bytes from buf to pmic-arb's register
+ * @bc byte-count -1. range: 0..3
+ * @reg register's address
+ * @buf buffer to write. length must be bc+1
On Tue, Oct 29, 2013 at 09:52:15AM -0700, Stephen Boyd wrote:
On 10/28/13 11:12, Josh Cartwright wrote:
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
new file mode 100644
index 000..a03835f
--- /dev/null
+++ b/drivers/spmi/Kconfig
@@ -0,0 +1,9 @@
+#
+# SPMI driver
On 10/30/13 12:37, Josh Cartwright wrote:
On Tue, Oct 29, 2013 at 09:52:15AM -0700, Stephen Boyd wrote:
On 10/28/13 11:12, Josh Cartwright wrote:
+int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf)
+{
+ /* 5-bit register address */
+ if (addr 0x1F)
Perhaps 0x1f should
Qualcomm's Krait CPUs have a handful of L2 cache controller
registers that live behind a cp15 based indirection register.
First you program the indirection register (l2cpselr) to point
the L2 'window' register (l2cpdr) at what you want to read/write.
Then you read/write the 'window' register to do
This allows us to probe the krait-edac driver.
Cc: David Brown dav...@codeaurora.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git
Add support for the Krait CPU cache error detection. This is a
simplified version of the code originally written by Stepan
Moskovchenko[1] ported to the EDAC device framework.
[1]
https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/mach-msm/cache_erp.c?h=msm-3.4
Cc: Stepan
We only setup a workqueue for edac devices that use the polling
method. We still try to cancel the workqueue if an edac_device
uses the irq method though. This causes a warning from debug
objects when we remove an edac device:
WARNING: CPU: 0 PID: 56 at lib/debugobjects.c:260
In the near future we're going to use these percpu irq functions
in the Krait CPU EDAC driver. Export them so that the EDAC driver
can be compiled as a module.
Acked-by: Thomas Gleixner t...@linutronix.de
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
kernel/irq/manage.c | 2 ++
1 file
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd
On Wed, Oct 30, 2013 at 01:25:36PM -0700, Stephen Boyd wrote:
This allows us to probe the krait-edac driver.
Cc: David Brown dav...@codeaurora.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 37 +
1 file changed,
On Tue, Oct 29, 2013 at 10:56:03AM -0700, Stephen Boyd wrote:
On 10/25, Andy Gross wrote:
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f238cfd..a71b415 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -364,4 +364,13 @@ config DMATEST
Simple DMA test
On 10/30/13 13:31, Andy Gross wrote:
On Tue, Oct 29, 2013 at 10:56:03AM -0700, Stephen Boyd wrote:
On 10/25, Andy Gross wrote:
+#include linux/scatterlist.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_irq.h
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc:
On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
On 10/30/13 14:45, Kumar Gala wrote:
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
@@ -75,3 +77,50 @@ Example:
reg = 0x101;
};
};
+
+If the compatible string contains qcom,krait there shall be an
On 10/30/13 14:56, Kumar Gala wrote:
On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
On 10/30/13 14:45, Kumar Gala wrote:
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
+l2-cache node containing the following properties:
Is the L1 interrupt not per core L1 cache (even if they are OR
On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote:
On 10/30/13 14:56, Kumar Gala wrote:
On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
On 10/30/13 14:45, Kumar Gala wrote:
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
+l2-cache node containing the following properties:
Is the L1
Olof Johansson o...@lixom.net writes:
I would be very happy to take more code for the older Qualcomm chipset
to enable full functionality for them, but it's been my impression
that far from all that is needed to make it a useful platform is in
the upstream kernel, and there's been no signs of
On Wed, Oct 30, 2013 at 04:08:27PM -0700, Kevin Hilman wrote:
Olof Johansson o...@lixom.net writes:
I would be very happy to take more code for the older Qualcomm chipset
to enable full functionality for them, but it's been my impression
that far from all that is needed to make it a
On Wed, Oct 30, 2013 at 4:25 PM, Daniel Walker dwal...@fifo99.com wrote:
So the current users of those platforms are, what SOL ?
What users? Show me one.
-Olof
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On Wed, Oct 30, 2013 at 05:36:58PM -0700, Olof Johansson wrote:
On Wed, Oct 30, 2013 at 4:25 PM, Daniel Walker dwal...@fifo99.com wrote:
So the current users of those platforms are, what SOL ?
What users? Show me one.
What am I chop liver ?
Daniel
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On Wed, Oct 30, 2013 at 7:45 PM, Daniel Walker dwal...@fifo99.com wrote:
On Wed, Oct 30, 2013 at 05:36:58PM -0700, Olof Johansson wrote:
On Wed, Oct 30, 2013 at 4:25 PM, Daniel Walker dwal...@fifo99.com wrote:
So the current users of those platforms are, what SOL ?
What users? Show me one.
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