Adds support for RTC device inside PM8941 PMIC. The RTC
in this PMIC have two register spaces. Thus the rtc-pm8xxx
is slightly reworked to reflect these differences.
The register set for different PMIC chips are selected
on DT compatible string base.
Signed-off-by: Stanimir Varbanov
2014-09-12 4:02 GMT+02:00 Wang, Yalin yalin.w...@sonymobile.com:
What's your @memory parameters in your dtb file?
And what's your PHYSICAL_OFFSET of your kexec kernel ?
TEXT_OFFSET is 0x8000;
Here's the content of the memory node:
memory {
#address-cells = 0x1;
On 09/11/14 18:56, Rob Herring wrote:
On Thu, Sep 11, 2014 at 5:14 PM, Stephen Boyd sb...@codeaurora.org wrote:
Add support for DT based early console on platforms with the msm
serial hardware.
Cc: Rob Herring r...@kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
One comment, but
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
This work was started by Ivan Ivanov and went through a number of iterations. I
picked these patches up and did a little rework to get them working.
Changes
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
From: Ivan T. Ivanov iiva...@mm-sol.com
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Hi,
On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross
On Fri, Sep 12, 2014 at 12:47:04PM -0500, Felipe Balbi wrote:
Hi,
On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with
On Fri, Sep 12, 2014 at 12:50:23PM -0500, Josh Cartwright wrote:
Hey Andy-
Mostly cosmetic things below:
On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
some
Qualcomm platforms. This driver uses the
Yay nitpicks!
On 09/12/14 10:29, Andy Gross wrote:
+
+struct qcom_dwc3_usb_phy {
+ void __iomem*base;
+ struct device *dev;
+ struct phy *phy;
Align with other members?
+
+static int wait_for_latch(void __iomem *addr)
+{
+ u32 retry = 10;
Why not
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile
From: Ivan T. Ivanov iiva...@mm-sol.com
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
This work was started by Ivan Ivanov and went through a number of iterations. I
picked these patches up and did a little rework to get them working.
Changes
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
The following changes since commit 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9:
Linux 3.17-rc1 (2014-08-16 10:40:26 -0600)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
tags/qcom-dt-for-3.18
for you to fetch changes up to
On Sat, Sep 13, 2014 at 01:44:25AM +0530, Pramod Gurav wrote:
Andy,
Couple of minor comments.
On Sat, Sep 13, 2014 at 12:58 AM, Andy Gross agr...@codeaurora.org wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its
Hi Felipe,
On 13-09-2014 01:50 AM, Felipe Balbi wrote:
On Sat, Sep 13, 2014 at 01:44:25AM +0530, Pramod Gurav wrote:
Andy,
Couple of minor comments.
On Sat, Sep 13, 2014 at 12:58 AM, Andy Gross agr...@codeaurora.org wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is
Hi,
On Sat, Sep 13, 2014 at 01:55:50AM +0530, Pramod Gurav wrote:
+ qdwc = devm_kzalloc(pdev-dev, sizeof(*qdwc), GFP_KERNEL);
+ if (!qdwc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, qdwc);
+
+ qdwc-dev = pdev-dev;
+
+
On 13-09-2014 01:59 AM, Felipe Balbi wrote:
Hi,
On Sat, Sep 13, 2014 at 01:55:50AM +0530, Pramod Gurav wrote:
+ qdwc = devm_kzalloc(pdev-dev, sizeof(*qdwc), GFP_KERNEL);
+ if (!qdwc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, qdwc);
+
+
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC accessible across
SPMI bus.
The vadc driver registers itself through IIO interface.
Looks already pretty good. Things you
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
Document DT binding for Qualcomm SPMI PMIC voltage ADC
driver.
Still one typo left.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
Do you pass a initrd to kexec kernel?
i don't see it.
- 发送自我的Sony Xperia™智能手机
Noé RUBINSTEIN编写
2014-09-12 4:02 GMT+02:00 Wang, Yalin yalin.w...@sonymobile.com:
What's your @memory parameters in your dtb file?
And what's your PHYSICAL_OFFSET of your kexec kernel ?
TEXT_OFFSET is
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