Hi,
On Sunday 14 September 2014 07:54 AM, Felipe Balbi wrote:
Hi,
On Sat, Sep 13, 2014 at 12:16:01PM +0530, Kishon Vijay Abraham I wrote:
On Saturday 13 September 2014 12:58 AM, Andy Gross wrote:
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
some
Qualcomm
On Mon, Sep 15, 2014 at 01:11:14PM +0800, Wang, Yalin wrote:
this patch extend the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page
Hi
I tested it on my phone,
From log:
4[0.00] INITRD unalign phys address:0x0200+0x0022fb0e
4[0.00] INITRD aligned phys address:0x0200+0x0023
4[0.579474] free_initrd_mem: free pfn:8192---8752
The tail address is not aligned for most initrd image,
This page will
On Mon, Sep 15, 2014 at 05:07:53PM +0800, Wang, Yalin wrote:
Hi
I tested it on my phone,
From log:
4[0.00] INITRD unalign phys address:0x0200+0x0022fb0e
4[0.00] INITRD aligned phys address:0x0200+0x0023
4[0.579474] free_initrd_mem: free pfn:8192---8752
Hi
Add more log:
4[0.00] INITRD unalign phys address:0x0200+0x0022fb0e
4[0.00] INITRD aligned phys address:0x0200+0x0023
4[0.574868] free_initrd: free initrd 0xc200+0xc222fb0e
4[0.579398] free_initrd_mem: free pfn:8192---8752
The inird used memory is still
Hi
Oh, I see your meaning,
Yeah , my initrd is a cpio image,
And it can still work after apply this patch.
-Original Message-
From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk]
Sent: Monday, September 15, 2014 6:17 PM
To: Wang, Yalin
Cc: 'Will Deacon';
On Mon, Sep 15, 2014 at 06:22:12PM +0800, Wang, Yalin wrote:
Oh, I see your meaning,
Yeah , my initrd is a cpio image,
And it can still work after apply this patch.
Okay, that's what I wanted to know. However, I believe your patch to
be incorrect. You delete the assignments to initrd_start
2014-09-10 20:54 GMT+09:00 Dolev Raviv dra...@codeaurora.org:
+static void ufshcd_set_queue_depth(struct scsi_device *sdev)
+{
+ int ret = 0;
+ u8 lun_qdepth;
+ struct ufs_hba *hba;
+
+ hba = shost_priv(sdev-host);
+
+ lun_qdepth = hba-nutrs;
+ ret =
Oh, I see,
I don't consider non-of platform kernels,
I will send V2 patch for this .
Thanks
-Original Message-
From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk]
Sent: Monday, September 15, 2014 6:30 PM
To: Wang, Yalin
Cc: 'Will Deacon'; 'linux-ker...@vger.kernel.org';
this patch extend the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page can't be freed by free_initrd_mem() function.
Signed-off-by:
2014-09-10 20:54 GMT+09:00 Dolev Raviv dra...@codeaurora.org:
+static inline void ufshcd_enable_irq(struct ufs_hba *hba)
+{
+ if (!hba-is_irq_enabled) {
+ enable_irq(hba-irq);
+ hba-is_irq_enabled = true;
+ }
+}
+
+static inline void
On Mon, Sep 15, 2014 at 07:07:20PM +0800, Wang, Yalin wrote:
this patch extend the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page
Hi Jonathan,
Thanks for the review!
On 09/13/2014 08:27 PM, Jonathan Cameron wrote:
On 13/09/14 00:27, Hartmut Knaack wrote:
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC
Thanks for the comments!
On 09/13/2014 02:27 AM, Hartmut Knaack wrote:
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC accessible across
SPMI bus.
The vadc driver registers
Great!
yeah, you are right,
just keep the change in free_initrd_mem( ) is ok.
we don't need keep reserved memory to be aligned ,
Thanks!
From: Russell King - ARM Linux [li...@arm.linux.org.uk]
Sent: Monday, September 15, 2014 7:33 PM
To: Wang, Yalin
Cc:
Hi,
This is forth version of the patches posted earlier here[1].
Changes:
- Driver for SSBI PMIC dropped from this patchest - let Bjorn to handle it.
- Separate MPP and GPIO drivers.
- Second value in 'reg' propriety is used to specify address range length
and this number of GPIO/MPP's that
DeviceTree binding documentation for Qualcomm SPMI PMIC MPP
pinctrl drivers.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 159 +
include/dt-bindings/pinctrl/qcom,pmic-mpp.h| 44 ++
2 files changed, 203
From: Bjorn Andersson bjorn.anders...@sonymobile.com
This introduced the device tree bindings for the GPIO block found
in PMIC's from Qualcomm.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm MPP sub-function blocks found in the PMIC chips.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-spmi-pmic-mpp.c | 956
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm GPIO sub-function blocks found in the PMIC chips.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/pinctrl/qcom/Kconfig | 12 +
drivers/pinctrl/qcom/Makefile | 1 +
2014-09-15 19:39 GMT+09:00 Dolev Raviv dra...@codeaurora.org:
2014-09-10 20:54 GMT+09:00 Dolev Raviv dra...@codeaurora.org:
+static void ufshcd_set_queue_depth(struct scsi_device *sdev)
+{
+ int ret = 0;
+ u8 lun_qdepth;
+ struct ufs_hba *hba;
+
+ hba =
Add support for the temperature alarm peripheral found inside
Qualcomm plug-and-play (QPNP) PMIC chips. The temperature alarm
peripheral outputs a pulse on an interrupt line whenever the
thermal over temperature stage value changes. Implement an ISR
to manage this interrupt.
Register a thermal
Hey Ivan,
Please give us at least a two weeks time frame before resending your
patches.
On Mon, Sep 15, 2014 at 06:03:03PM +0300, Ivan T. Ivanov wrote:
Add support for the temperature alarm peripheral found inside
Qualcomm plug-and-play (QPNP) PMIC chips. The temperature alarm
peripheral
Hi,
On 09/15/2014 06:03 PM, Ivan T. Ivanov wrote:
Add support for the temperature alarm peripheral found inside
Qualcomm plug-and-play (QPNP) PMIC chips. The temperature alarm
peripheral outputs a pulse on an interrupt line whenever the
thermal over temperature stage value changes.
On September 15, 2014 3:12:50 PM GMT+01:00, Stanimir Varbanov
svarba...@mm-sol.com wrote:
Hi Jonathan,
Thanks for the review!
On 09/13/2014 08:27 PM, Jonathan Cameron wrote:
On 13/09/14 00:27, Hartmut Knaack wrote:
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
The voltage ADC is
On 09/14/14 21:12, Andy Gross wrote:
static struct clk_pll pll3 = {
.l_reg = 0x3164,
.m_reg = 0x3168,
@@ -155,6 +182,7 @@ static const char *gcc_pxo_pll8_pll0_map[] = {
pxo,
pll8_vote,
pll0,
+ pll0_vote,
};
This is wrong. We should be removing pll0 and
On 09/04/14 15:01, Stephen Boyd wrote:
8
From: Stephen Boyd sb...@codeaurora.org
Subject: [PATCH] mmc: Consolidate emmc tuning blocks
The same tuning block array exists in the dw_mmc h.c and sdhci-msm.c
files. Move these into mmc.c so that they can be shared across
drivers.
Add support for DT based and command line based early console on platforms
with the msm serial hardware.
Cc: Rob Herring r...@kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
Changes since v1:
* Add kernel commandline support
Documentation/kernel-parameters.txt | 12 ++
this patch extend the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page can't be freed by free_initrd_mem() function.
Signed-off-by:
On Sep 9, 2014, at 8:36 AM, Kumar Gala ga...@codeaurora.org wrote:
Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
(reposted with Hans on list)
v4:
* Updated to upstream changes
drivers/ata/ahci.h | 2 +-
1
On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
It also adds necessary DT support for i2c eeprom which is present on
IFC6410.
Tested on IFC6410 board.
Looks fine
Signed-off-by: Kiran Padwal
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