This patch extends the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page can't be freed by free_initrd_mem() function.
Signed-off-by:
Add compatible string for BAM v1.3.0 in the DT bindings documentation. Mentioned
a few more SoCs which have BAM v1.4.0 in them.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
Documentation/devicetree/bindings/dma/qcom_bam_dma.txt | 4 +++-
1 file changed,
We currently have register offset information only for BAM IPs with revision
1.4.0. We add register offset table entries for the legacy (v1.3.0) version
of BAM IPs found on SoCs like APQ8064 and MSM8960.
The register offset table pointers are stored in DT data corresponding to the
BAM IP version
Hi Dolev,
On Wednesday 10 September 2014 05:24 PM, Dolev Raviv wrote:
From: Subhash Jadavani subha...@codeaurora.org
This patch adds support for UFS device and UniPro link power management
during runtime/system PM.
snip
+vccq_lpm:
+ ufshcd_config_vreg_lpm(hba, hba-vreg_info.vccq);
On Wednesday 10 September 2014 05:24 PM, Dolev Raviv wrote:
From: Sahitya Tummala stumm...@codeaurora.org
The UFS controller clocks can be gated after certain period of
inactivity, which is typically less than runtime suspend timeout.
In addition to clocks the link will also be put into
The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
16 bits resolution and register space inside PMIC accessible across
SPMI bus.
The driver registers itself through IIO interface.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
On 18/09/14 05:37, Bjorn Andersson wrote:
On Wed, Sep 17, 2014 at 2:49 PM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
On 17/09/14 20:18, Josh Cartwright wrote:
On Wed, Sep 17, 2014 at 12:03:37PM -0700, Kumar Gala wrote:
[..]
Hmm, this doesn?t seem to work for me.
I
On Thu, Sep 18, 2014 at 07:53:57AM +0100, Wang, Yalin wrote:
This patch extends the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page
If those are the only LUs you specificly need I'd suggest you just
manually call scsi_add_device from your driver for those instead of listing
them in REPORT_LUNS and making them part of the normal LUN scan.
Yes, we can do that but not sure what would be advantage of making the LLDs
to add
On Tue 16 Sep 16:14 PDT 2014, Tim Bird wrote:
On 09/16/2014 04:08 PM, Kumar Gala wrote:
On Sep 16, 2014, at 4:03 PM, Tim Bird tim.b...@sonymobile.com wrote:
[..]
+ qcom,msm-id = 126 8 0, 185 8 0, 186 8 0;
We don’t have qcom,msm-id upstream at this time.
Do I just leave this
Hi Chris,
While testing with another vendor's UFS devices, I realized that SELECT
REPORT need not to be set to 0x02 for making the device report the W-LUs.
Even when SELECT REPORT is set 0x00, this particular UFS device reports the
W-LUs so I looked at the SCSI specification in details and it
These changes allow us to support VFP correctly on Krait processors.
They also fix short vector emulation for Cortex-A15 and Krait.
Stepan Moskovchenko (1):
arm: vfp: Bounce undefined instructions in vectored mode
Stephen Boyd (2):
ARM: vfp: Workaround bad MVFR1 register on some Kraits
Certain versions of the Krait processor don't report that they
support the fused multiply accumulate instruction via the MVFR1
register despite the fact that they actually do. Unfortunately we
use this register to identify support for VFPv4. Override the
hwcap on all Krait processors to indicate
From: Stepan Moskovchenko step...@codeaurora.org
Certain ARM CPU implementations (e.g. Cortex-A15) may not raise a
floating- point exception whenever deprecated short-vector VFP
instructions are executed. Instead these instructions are treated
as UNALLOCATED. Change the VFP exception handling
The subarchitecture field in the fpsid register is 7 bits wide.
The topmost bit is used to designate that the subarchitecture
designer is not ARM. We use this field to determine which VFP
version is supported by the CPU. Since the topmost bit is ignored
with the current mask we detect non-ARM
It would be nice to be copied on these patches, as the VFP code is
entirely my creation... I'll review these patches shortly.
On Thu, Sep 18, 2014 at 02:43:09PM -0700, Stephen Boyd wrote:
These changes allow us to support VFP correctly on Krait processors.
They also fix short vector emulation
This patchset provides support for the Watchdog Timer (WDT) found in the Krait
Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips.
This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary
interface is through userspace. The implemantion is currently very
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 10 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 145
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 21 +
1
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by:
On Thu, Sep 18, 2014 at 02:43:11PM -0700, Stephen Boyd wrote:
diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
index f4ab34fd4f72..76d3f6907cce 100644
--- a/arch/arm/include/asm/vfp.h
+++ b/arch/arm/include/asm/vfp.h
@@ -21,7 +21,7 @@
#define FPSID_FORMAT_MASK(0x3
On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Choose priority 128, as
On Thu, Sep 18, 2014 at 03:47:20PM -0700, Kumar Gala wrote:
On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where
On Sep 18, 2014, at 3:49 PM, Josh Cartwright jo...@codeaurora.org wrote:
On Thu, Sep 18, 2014 at 03:47:20PM -0700, Kumar Gala wrote:
On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other
Hi Andy,
Does this patchset supersede dmaengine: qcom_bam_dma: Add v1.3.0 ...
https://lkml.org/lkml/2014/4/16/660
--srini
On 18/09/14 11:52, Archit Taneja wrote:
The BAM DMA IP comes in different versions. The register offset layout varies
among these versions. The layouts depend on which
On Thu, Sep 18, 2014 at 11:55:31PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 18, 2014 at 02:43:12PM -0700, Stephen Boyd wrote:
From: Stepan Moskovchenko step...@codeaurora.org
Certain ARM CPU implementations (e.g. Cortex-A15) may not raise a
floating- point exception whenever
On 09/18/2014 03:27 PM, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the
On 09/18/2014 03:32 PM, Josh Cartwright wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Choose priority 128, as according to documentation, this
On Thu, Sep 18, 2014 at 07:41:17PM -0700, Guenter Roeck wrote:
On 09/18/2014 03:26 PM, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
On 09/18/2014 07:54 PM, Guenter Roeck wrote:
On 09/18/2014 03:32 PM, Josh Cartwright wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Choose
On Thu, Sep 18, 2014 at 07:47:54PM -0700, Guenter Roeck wrote:
On 09/18/2014 03:27 PM, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for
On 09/18/2014 08:24 PM, Josh Cartwright wrote:
On Thu, Sep 18, 2014 at 07:41:17PM -0700, Guenter Roeck wrote:
On 09/18/2014 03:26 PM, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
On 09/18/2014 08:32 PM, Josh Cartwright wrote:
On Thu, Sep 18, 2014 at 07:47:54PM -0700, Guenter Roeck wrote:
On 09/18/2014 03:27 PM, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
On 09/18/2014 03:26 PM, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Hi Josh,
comments inline.
Thanks,
Guenter
---
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