RE: [PATCH] drm/msm: Don't split an IB at the end of ring buffer.

Hi Ganesan, On Thursday, October 30, 2014 10:33pm, "Ganesan, Aravind" said: > Splitting the command sequence for an IB1 submission at the end of > the ring buffer can hang the GPU. To fix this, if there isn't > enough contiguous space at the end to fit the full command sequence, > insert NOPs

[PATCH] ARM: Update processor_modes for hyp and monitor mode

If the kernel is running in hypervisor mode or monitor mode we'll print UK6_32 or UK10_32 if we call into __show_regs(). Let's update these strings to indicate the new modes that didn't exist when this code was written. Signed-off-by: Stephen Boyd --- arch/arm/kernel/process.c | 4 ++-- 1 file c

Re: [PATCH v9 6/9] qcom: cpuidle: Add cpuidle driver for QCOM cpus

On Mon, Nov 17 2014 at 10:39 -0700, Lorenzo Pieralisi wrote: On Sat, Oct 25, 2014 at 12:40:21AM +0100, Lina Iyer wrote: Add cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface, common across ARM architectures, to provide the C-State information to the cpuidle

Re: [PATCH v4 2/2] iio: vadc: Qualcomm SPMI PMIC voltage ADC driver

Ivan T. Ivanov schrieb am 12.11.2014 09:55: > > On Tue, 2014-11-11 at 23:39 +0100, Hartmut Knaack wrote: >> Ivan T. Ivanov schrieb am 11.11.2014 09:21: >>> Hi Hartmut, >>> >>> On Mon, 2014-11-10 at 22:11 +0100, Hartmut Knaack wrote: Ivan T. Ivanov schrieb am 03.11.2014 16:24: > From: Stan

Re: [PATCH] drm/msm/mdp5: get the core clock rate from MDP5 config

On Mon, Nov 17, 2014 at 1:39 PM, Stephane Viau wrote: > The core clock rate depends on the hw configuration. Once we have > read the hardware revision, we can set the core clock to its > maximum value. > Before then, the clock is set at a rate supported by all MDP5 > revisions. > > Signed-off-by:

[RFC] drm/msm/mdp5: use irqdomains

For mdp5, the irqs of hdmi/eDP/dsi0/dsi1 blocks get routed through the mdp block. In order to decouple hdmi/eDP/etc, register an irq domain in mdp5. When hdmi/dsi/etc are used with mdp4, they can directly setup their irqs in their DT nodes as normal. When used with mdp5, instead set the mdp devi

Re: [PATCH v9 2/9] qcom: spm: Add Subsystem Power Manager driver

On 10/25/2014 01:40 AM, Lina Iyer wrote: Hi Lina, [ ... ] +static inline void spm_register_write(struct spm_driver_data *drv, + enum spm_reg reg, u32 val) +{ + if (drv->reg_data->reg_offset[reg]) + writel_relaxed(val, drv->reg_base + +

[PATCH] drm/msm/mdp5: get the core clock rate from MDP5 config

The core clock rate depends on the hw configuration. Once we have read the hardware revision, we can set the core clock to its maximum value. Before then, the clock is set at a rate supported by all MDP5 revisions. Signed-off-by: Stephane Viau --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 9

Re: [PATCH v9 6/9] qcom: cpuidle: Add cpuidle driver for QCOM cpus

On Sun, Nov 16 2014 at 14:20 -0700, Daniel Lezcano wrote: On 10/25/2014 01:40 AM, Lina Iyer wrote: Add cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface, common across ARM architectures, to provide the C-State information to the cpuidle framework. Supporte

Re: [PATCH v9 6/9] qcom: cpuidle: Add cpuidle driver for QCOM cpus

On Sat, Oct 25, 2014 at 12:40:21AM +0100, Lina Iyer wrote: > Add cpuidle driver interface to allow cpus to go into C-States. Use the > cpuidle DT interface, common across ARM architectures, to provide the > C-State information to the cpuidle framework. "idle states", this is not ACPI. > Supported

Re: [PATCH] clk: qcom: Fix duplicate rbcpr clock name

On 10/11/2014 03:16 AM, Stephen Boyd wrote: > On 10/10, Georgi Djakov wrote: >> There is a duplication in a clock name for apq8084 platform that causes >> the following warning: "RBCPR_CLK_SRC" redefined >> >> Resolve this by adding a MMSS_ prefix to this clock and making its name >> coherent with