Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20 +++
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
Acked
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 16 +
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
implementation file.
Signed-off-by: Lina Iyer
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v12:
- Minor fixes
- Added Reviewed-by
Changes since v11:
- Address review comments on
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
On 11/17/2014 05:05 PM, Stephen Boyd wrote:
If the kernel is running in hypervisor mode or monitor mode we'll
print UK6_32 or UK10_32 if we call into __show_regs(). Let's
update these strings to indicate the new modes that didn't exist
when this code was written.
Signed-off-by: Stephen Boyd
---
On 11/26/2014 05:40 AM, Mark Brown wrote:
On Tue, Nov 25, 2014 at 05:02:52PM -0800, Stephen Boyd wrote:
On 11/25/2014 12:44 PM, Mark Brown wrote:
I can't help but think that this all sounds like the RPM isn't mapping
very well onto practical systems and needs revisiting in future
versions...
On 11/25/2014 02:07 PM, Mark Brown wrote:
> On Wed, Nov 19, 2014 at 10:52:47AM -0800, Kenneth Westfield wrote:
>
>> +++ b/sound/soc/qcom/Kconfig
>> @@ -0,0 +1,43 @@
...
>> +# Permission to use, copy, modify, and/or distribute this software for any
>> +# purpose with or without fee is hereby grante
On Wed, Nov 26 2014 at 17:53 -0700, Kevin Hilman wrote:
Lina Iyer writes:
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The
On 11/26/2014 04:13 PM, Lina Iyer wrote:
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
imple
Lina Iyer writes:
> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core executes WFI instruction,
> the SPM takes over the putting the core in low power state as
> configured. The wake up for the SPM is an interrupt at the GIC, wh
On Wed, Nov 26 2014 at 17:13 -0700, Lina Iyer wrote:
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 16 +
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20 +++
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
implementation file.
Signed-off-by: Lina Iyer
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
Acked
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v11:
- Address review comments on spm.c
- Commenting style fixes
- Added Reviewed-by
Ch
On Wed, Nov 26, 2014 at 12:15 PM, Jilai Wang wrote:
> HPD interrupt can be tracked for each connector, so don't need
> to poll the connector status for state change.
>
> Change-Id: I2c062838af5922d32ce87a50676a45dcaedb44f2
Please remove the Change-Id when sending patches to the kernel.
Regards,
On Wed, Nov 26 2014 at 15:42 -0700, Stephen Boyd wrote:
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance
On Tue 25 Nov 12:44 PST 2014, Mark Brown wrote:
> On Mon, Nov 24, 2014 at 01:19:47PM -0800, Stephen Boyd wrote:
> > On 11/24/2014 10:16 AM, Mark Brown wrote:
[..]
> > respectively. The RPM regulator driver aggregates the active set for
> > both the regulators via a max() operation and sends that
On Mon 24 Nov 16:02 PST 2014, Stephen Boyd wrote:
> On 11/24/2014 01:59 PM, Bjorn Andersson wrote:
> > On Mon 24 Nov 13:19 PST 2014, Stephen Boyd wrote:
> >
> > [..]
> >> What exactly are we circumventing? I can only guess that we're talking
> >> about the aggregation logic?
> >>
> > We're circumv
On 11/26/2014 02:28 PM, Lina Iyer wrote:
+
+static struct platform_driver qcom_cpuidle_plat_driver = {
+ .probe = qcom_cpuidle_probe,
+ .driver = {
+ .name = "qcom_cpuidle",
+ },
+};
+
+module_platform_driver(qcom_cpuidle_plat_driver);
Said this a few reviews ag
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by:
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
imple
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 16 +
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20 +++
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
Acked
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 26
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v10:
[ https://www.mail-archive.com/devicetree@vger.kernel.org/msg51880.html ]
- Address
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
implementation file.
Signed-off-by: Lina Iyer
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660,
8960 and 8064 based devices.
Signed-off-by: Bjorn Andersson
---
Removed regulator definition from this patch, as these needs more discussion to
be able to implement SoC assisted power save features of the Qualcomm
platforms
This adds the missing state parameter to the call down to the RPM. This
is currently hard coded to the active state, as that's all we're
supporting at this moment.
Signed-off-by: Bjorn Andersson
---
drivers/regulator/qcom_rpm-regulator.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/driver
Driver for the Resource Power Manager (RPM) found in Qualcomm 8660, 8960
and 8064 based devices. The driver exposes resources that child drivers
can operate on; to implementing regulator, clock and bus frequency
drivers.
Signed-off-by: Bjorn Andersson
---
Lee, since your Acked-by earlier I've fo
In order to support the SoC assisted power save features of the Qualcomm
platform some changes are most likely needed to the regulator part of the DT
bindings provided before.
This version of the patchset carries the RPM core part, which allows us to move
forward with merging Josh's patches [1] as
On 11/26/2014 07:04 PM, Kevin Hilman wrote:
Oops, I thought I had sent this, but it was sitting in the drafts
folder. Sending anyways because it looks like most of these issues
still exist in v10.
[ ... ]
+* On some SoC's if the control registers are written first and if the
+
On Wed, Nov 26 2014 at 10:59 -0700, Lorenzo Pieralisi wrote:
On Fri, Nov 21, 2014 at 06:03:54PM +, Lina Iyer wrote:
Add cpuidle driver interface to allow cpus to go into C-States. Use the
"idle states" please.
Sorry. Done.
Acked-by: Lorenzo Pieralisi
--
To unsubscribe from this list:
clock driver can support dynamic rate settings for HDMI
pixelclock, so don't need to use clk_round_rate to check if the
clockrate for specific mode is supported therefore more display
modes can be supported.
Change-Id: I308df4eb604438c24df463619571d8e18cc956b6
Signed-off-by: Jilai Wang
---
drive
On 11/21/2014 10:03 AM, Lina Iyer wrote:
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
With nitpick addressed:
Reviewed-by
Disable the HPD interrupt when acking it, to avoid spurious
interrupt.
Change-Id: Icb64d7fa813380c7ffa3047058503ebab13ff4c4
Signed-off-by: Jilai Wang
---
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi
On 11/21/2014 10:03 AM, Lina Iyer wrote:
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
-
HPD regulators need to be enabled before clocks, otherwise clock
driver will report warning.
Change-Id: Ieca41722ae3b15873e6290649a21bbd13e1a4278
Signed-off-by: Jilai Wang
---
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 45 +--
1 file changed, 18 insertions(+), 27 del
On 11/21/2014 10:03 AM, Lina Iyer wrote:
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
--
Qua
HPD interrupt can be tracked for each connector, so don't need
to poll the connector status for state change.
Change-Id: I2c062838af5922d32ce87a50676a45dcaedb44f2
Signed-off-by: Jilai Wang
---
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
di
On 11/21/2014 10:03 AM, Lina Iyer wrote:
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
--
Qu
On 11/21/2014 10:03 AM, Lina Iyer wrote:
@@ -144,7 +148,27 @@
};
};
- saw_l2: regulator@f9012000 {
+ saw0: power-controller@f9089000 {
+ compatible = "qcom,apq8084-saw2-v2.1-cpu";
+ reg = <0xf90
On 11/21/2014 10:03 AM, Lina Iyer wrote:
@@ -144,7 +148,27 @@
};
};
- saw_l2: regulator@f9012000 {
+ saw0: power-controller@f9089000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu";
+ reg = <0xf90
On 11/21/2014 10:03 AM, Lina Iyer wrote:
+
+static const struct platform_device_info qcom_cpuidle_info = {
nitpick, why two spaces between info and qcom here?
+ .name = "qcom_cpuidle",
+ .id = -1,
+ .data = &lpm_ops,
+ .size_data = sizeof(lpm_ops),
+};
This st
On Wed, Nov 26 2014 at 12:48 -0700, Stephen Boyd wrote:
On 11/21/2014 10:03 AM, Lina Iyer wrote:
@@ -37,3 +54,17 @@ int scm_set_boot_addr(phys_addr_t addr, int flags)
&cmd, sizeof(cmd), NULL, 0);
}
EXPORT_SYMBOL(scm_set_boot_addr);
+
+int scm_set_warm_boot_addr(void *en
On 11/21/2014 10:03 AM, Lina Iyer wrote:
@@ -37,3 +54,17 @@ int scm_set_boot_addr(phys_addr_t addr, int flags)
&cmd, sizeof(cmd), NULL, 0);
}
EXPORT_SYMBOL(scm_set_boot_addr);
+
+int scm_set_warm_boot_addr(void *entry, int cpu)
+{
+ int ret;
+
+ if (entry =
Daniel Lezcano writes:
> On 11/21/2014 07:03 PM, Lina Iyer wrote:
>> Add cpuidle driver interface to allow cpus to go into C-States. Use the
>> cpuidle DT interface, common across ARM architectures, to provide the
>> idle state information to the cpuidle framework.
>>
>> Supported modes at this t
On 11/21/2014 10:03 AM, Lina Iyer wrote:
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code A
Oops, I thought I had sent this, but it was sitting in the drafts
folder. Sending anyways because it looks like most of these issues
still exist in v10.
Lina Iyer writes:
> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core exe
On Fri, Nov 21, 2014 at 06:03:54PM +, Lina Iyer wrote:
> Add cpuidle driver interface to allow cpus to go into C-States. Use the
"idle states" please.
> cpuidle DT interface, common across ARM architectures, to provide the
> idle state information to the cpuidle framework.
>
> Supported mode
On Tue, Nov 25, 2014 at 11:55 AM, Timur Tabi wrote:
> On Thu, Dec 5, 2013 at 8:10 PM, Bjorn Andersson
> wrote:
>>
>> +static int msm_gpio_init(struct msm_pinctrl *pctrl)
>> +{
>> + struct gpio_chip *chip;
>> + int irq;
>> + int ret;
>> + int i;
>> + int r;
>> +
>> +
On Wed, Nov 26 2014 at 08:20 -0700, Lina Iyer wrote:
On Wed, Nov 26 2014 at 04:19 -0700, Daniel Lezcano wrote:
On 11/19/2014 06:43 PM, Lina Iyer wrote:
On Fri, Nov 14 2014 at 08:56 -0700, Daniel Lezcano wrote:
On 10/25/2014 01:40 AM, Lina Iyer wrote:
+
+if ((cpu > -1) && !cpuidle_drv_
On Wed, Nov 26 2014 at 04:19 -0700, Daniel Lezcano wrote:
On 11/19/2014 06:43 PM, Lina Iyer wrote:
On Fri, Nov 14 2014 at 08:56 -0700, Daniel Lezcano wrote:
On 10/25/2014 01:40 AM, Lina Iyer wrote:
+
+if ((cpu > -1) && !cpuidle_drv_init) {
+platform_device_register(&qcom_cpuidl
On Tue, Nov 25, 2014 at 05:02:52PM -0800, Stephen Boyd wrote:
> On 11/25/2014 12:44 PM, Mark Brown wrote:
> >I'm still quite confused here...
> Hm... hopefully it's not getting worse.
It is a bit, the story keeps changing a lot.
> >I can't help but think that this all sounds like the RPM isn't
On 11/19/2014 06:43 PM, Lina Iyer wrote:
On Fri, Nov 14 2014 at 08:56 -0700, Daniel Lezcano wrote:
On 10/25/2014 01:40 AM, Lina Iyer wrote:
+/**
+ * spm_set_low_power_mode() - Configure SPM start address for low
power mode
+ * @mode: SPM LPM mode to enter
+ */
+int qcom_spm_set_low_power_mode
On 11/21/2014 07:03 PM, Lina Iyer wrote:
Add cpuidle driver interface to allow cpus to go into C-States. Use the
cpuidle DT interface, common across ARM architectures, to provide the
idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Co
On 11/21/2014 07:03 PM, Lina Iyer wrote:
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
imple
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