On Fri, Jun 19, 2015 at 05:28:53PM -0500, Timur Tabi wrote:
> On 06/15/2015 05:59 AM, Catalin Marinas wrote:
> >I think this patch together with the second one could go through the kvm
> >tree. For the core arm64 part:
> >
> >Acked-by: Catalin Marinas
>
> Suzuki
Timur Tabi
I think this patch together with the second one could go through the kvm
tree. For the core arm64 part:
Acked-by: Catalin Marinas
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On Thu, Apr 16, 2015 at 01:17:32PM -0400, Rob Clark wrote:
> On Thu, Apr 16, 2015 at 11:21 AM, Catalin Marinas
> wrote:
> > On Wed, Apr 15, 2015 at 11:01:17AM -0400, Rob Clark wrote:
> >> There are folks who are working to get saner, more-upstream kernels
> >> work
On Wed, Apr 15, 2015 at 11:01:17AM -0400, Rob Clark wrote:
> On Wed, Apr 15, 2015 at 9:34 AM, Catalin Marinas
> wrote:
> > On Tue, Apr 14, 2015 at 05:48:48PM -0400, Rob Clark wrote:
> >> Just speaking as an outsider to this topic, but seems like most/all
> >> table
On Wed, Apr 15, 2015 at 10:04:25AM +0100, Mark Rutland wrote:
> On Tue, Apr 14, 2015 at 11:52:39PM +0100, Al Stone wrote:
> > On 04/14/2015 10:29 AM, Mark Rutland wrote:
> > >> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
> > >> b/Documentation/devicetree/bindings/arm/cpus.txt
> > >
On Tue, Apr 14, 2015 at 10:51:40PM +0200, Arnd Bergmann wrote:
> On Tuesday 14 April 2015 17:29:53 Mark Rutland wrote:
> > > +static int msm_cpu_boot(unsigned int cpu)
> > > +{
> > > + int ret = 0;
> > > +
> > > + if (per_cpu(cold_boot_done, cpu) == false) {
> > > + ret =
On Tue, Apr 14, 2015 at 09:21:17AM -0500, Kumar Gala wrote:
> On Apr 13, 2015, at 4:41 AM, Catalin Marinas wrote:
> > On Fri, Apr 10, 2015 at 02:06:33PM -0500, Kumar Gala wrote:
> >> On Apr 10, 2015, at 11:10 AM, Catalin Marinas
> >> wrote:
> >> Qualcom
On Tue, Apr 14, 2015 at 05:48:48PM -0400, Rob Clark wrote:
> Just speaking as an outsider to this topic, but seems like most/all
> tablets/phones/etc ship with signed firmware. Which means for most of
> the population, upgrading the firmware to a new version which did
> support the standard (assum
On Tue, Apr 14, 2015 at 02:49:04PM -0500, Kumar Gala wrote:
> On Apr 14, 2015, at 11:36 AM, Mark Rutland wrote:
> > On Fri, Apr 10, 2015 at 11:05:29AM +0100, Catalin Marinas wrote:
> >> On Thu, Apr 09, 2015 at 12:37:06PM -0500, Kumar Gala wrote:
> >>> This patch se
On Fri, Apr 10, 2015 at 02:06:33PM -0500, Kumar Gala wrote:
> On Apr 10, 2015, at 11:10 AM, Catalin Marinas wrote:
> > On Fri, Apr 10, 2015 at 10:24:46AM -0500, Kumar Gala wrote:
> >> On Apr 10, 2015, at 5:05 AM, Catalin Marinas
> >> wrote:
> >>> On Thu,
On Fri, Mar 13, 2015 at 10:34:54AM +, Mark Rutland wrote:
> > > Which of spin-table/psci are you planning on using for SMP support, and
> > > when would that be likely to appear?
> >
> > We have a qcom specific SMP enablement method for this device. This
> > was one of our first devices so it
nged, 9 insertions(+), 2 deletions(-)
>
> Any comments here? Perhaps I can send this through the patch tracker?
FWIW, they look fine to me.
Acked-by: Catalin Marinas
I guess the reason it works fine on other platforms is because the
secondary start address we pass to firmware has bit 0 se
On Fri, Dec 05, 2014 at 05:27:02PM +, Russell King - ARM Linux wrote:
> On Fri, Dec 05, 2014 at 05:07:45PM +0000, Catalin Marinas wrote:
> > From 8e317c6be00abe280de4dcdd598d2e92009174b6 Mon Sep 17 00:00:00 2001
> > From: Catalin Marinas
> > Date: Fri, 5 Dec 2014 16:41
On Fri, Dec 05, 2014 at 12:05:06PM +, Will Deacon wrote:
> On Thu, Dec 04, 2014 at 12:03:05PM +0000, Catalin Marinas wrote:
> > On Mon, Sep 15, 2014 at 12:33:25PM +0100, Russell King - ARM Linux wrote:
> > > On Mon, Sep 15, 2014 at 07:07:20PM +0800, Wang, Yalin wrote:
> &g
On Fri, Dec 05, 2014 at 02:35:29AM +, Wang, Yalin wrote:
> > -Original Message-
> > From: Catalin Marinas [mailto:catalin.mari...@arm.com]
> > Sent: Thursday, December 04, 2014 8:03 PM
> > To: Russell King - ARM Linux
> > Cc: Wang, Yalin; 'linux
On Mon, Sep 15, 2014 at 12:33:25PM +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 15, 2014 at 07:07:20PM +0800, Wang, Yalin wrote:
> > @@ -636,6 +646,11 @@ static int keep_initrd;
> > void free_initrd_mem(unsigned long start, unsigned long end)
> > {
> > if (!keep_initrd) {
> > +
On Mon, Dec 01, 2014 at 06:57:05PM +, Lina Iyer wrote:
> On Thu, Nov 27 2014 at 08:01 -0700, Lorenzo Pieralisi wrote:
> >On Thu, Nov 27, 2014 at 05:24:07AM +, Lina Iyer wrote:
> >
> >[...]
> >
> >> +static int spm_set_low_power_mode(enum pm_sleep_mode mode)
> >> +{
> >> + struct spm_d
Stephen,
On Tue, Oct 28, 2014 at 01:19:12AM +, Stephen Boyd wrote:
> Exporting all the different possible configurations of CPUID
> registers to userspace via hwcaps is going to explode the hwcaps.
> Emulate userspace cpuid register accesses and export a new
> "cpuid" hwcap instead so that use
On Thu, Sep 25, 2014 at 03:31:42PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 19, 2014 at 11:00:02AM +0100, Catalin Marinas wrote:
> > On Fri, Sep 19, 2014 at 08:09:47AM +0100, Wang, Yalin wrote:
> > > this patch extend the start and end address of initrd to be page
aligned, the page can't be freed by free_initrd_mem() function.
>
> Signed-off-by: Yalin Wang
Acked-by: Catalin Marinas
(as I said, if Russell doesn't have any objections please send the patch
to his patch system)
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aligned, the page can't be freed by free_initrd_mem() function.
>
> Signed-off-by: Yalin Wang
You still have a typo in the subject.
For the arm64 part:
Acked-by: Catalin Marinas
so you can merge it via Russell's patch system.
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On Wed, Apr 09, 2014 at 12:39:37AM +0100, Michael Bohan wrote:
> On Tue, Apr 08, 2014 at 12:49:49PM +0100, Catalin Marinas wrote:
> > On Tue, Apr 08, 2014 at 01:35:47AM +0100, Michael Bohan wrote:
> > > How should we handle Device Memory with copy_from_user / copy_to_user?
>
On Tue, Apr 08, 2014 at 01:35:47AM +0100, Michael Bohan wrote:
> On Fri, Feb 21, 2014 at 10:53:08AM +0000, Catalin Marinas wrote:
> > On Fri, Feb 21, 2014 at 09:58:27AM +, Zhou Zhu wrote:
> > > We faced one issue using memcpy for memory type DEVICE_nGnRnE
> > >
On Mon, Feb 10, 2014 at 03:25:34AM +, Laura Abbott wrote:
> On 2/6/2014 6:09 PM, Courtney Cavin wrote:
> > On Wed, Feb 05, 2014 at 01:02:31AM +0100, Laura Abbott wrote:
> >> memblock is now fully integrated into the kernel and is the prefered
> >> method for tracking memory. Rather than reinven
On Fri, Oct 04, 2013 at 12:43:40PM +0100, Russell King - ARM Linux wrote:
> On Thu, Oct 03, 2013 at 10:09:14AM -0700, Greg Kroah-Hartman wrote:
> > On Thu, Oct 03, 2013 at 09:46:30AM -0700, Olof Johansson wrote:
> > > I don't have a good answer though. If it wasn't for the arm64 fork,
> > > locatin
On Thu, Oct 03, 2013 at 06:54:07PM +0100, Olof Johansson wrote:
> On Thu, Oct 3, 2013 at 10:09 AM, Greg Kroah-Hartman
> wrote:
> > On Thu, Oct 03, 2013 at 09:46:30AM -0700, Olof Johansson wrote:
> >> I don't have a good answer though. If it wasn't for the arm64 fork,
> >> locating these under arch
On Mon, Jun 10, 2013 at 05:12:08AM +0100, Rob Herring wrote:
> On 06/04/2013 05:21 AM, Russell King - ARM Linux wrote:
> > On Mon, Jun 03, 2013 at 06:51:59PM -0700, Stephen Boyd wrote:
> >> On 06/03/13 15:12, Russell King - ARM Linux wrote:
> >>> If you have a 56-bit clock which ticks at a period o
On Wed, Jun 12, 2013 at 06:23:29PM +0100, Laura Abbott wrote:
> +int set_memory_ro(unsigned long addr, int numpages)
> +{
> + unsigned long start = addr;
> + unsigned long size = PAGE_SIZE*numpages;
> + unsigned end = start + size;
> +
> + apply_to_page_range(&init_mm, start, size,
d correcting the timestamps when
> the hardware returns a value instead of 0 upon the first read.
>
> Signed-off-by: Stephen Boyd
Looks ok.
Acked-by: Catalin Marinas
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On Mon, Apr 15, 2013 at 02:09:20PM +0100, Christopher Covington wrote:
> On 04/15/2013 07:43 AM, Catalin Marinas wrote:
> > On Mon, Apr 15, 2013 at 11:58:40AM +0100, Catalin Marinas wrote:
> >> On Mon, Apr 15, 2013 at 11:45:42AM +0100, Will Deacon wrote:
> >>> On M
On Mon, Apr 15, 2013 at 11:58:40AM +0100, Catalin Marinas wrote:
> On Mon, Apr 15, 2013 at 11:45:42AM +0100, Will Deacon wrote:
> > On Mon, Apr 15, 2013 at 11:11:59AM +0100, Catalin Marinas wrote:
> > > On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
&g
On Mon, Apr 15, 2013 at 11:45:42AM +0100, Will Deacon wrote:
> On Mon, Apr 15, 2013 at 11:11:59AM +0100, Catalin Marinas wrote:
> > On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
> > > For accurate accounting pass contextidr_thread_switch the prev
> &g
On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
> For accurate accounting pass contextidr_thread_switch the prev
> task pointer, since cpu_switch_to has at that point changed the
> the stack pointer.
>
> Signed-off-by: Christopher Covington
> ---
> arch/arm64/kernel/proces
On Tue, Nov 15, 2011 at 11:49:09PM +, Laura Abbott wrote:
> Ensure that memory hotplug can co-exist with kmemleak
> by taking the hotplug lock before scanning the memory
> banks.
>
> Signed-off-by: Laura Abbott
Thanks, the patch looks fine to me. I'll add it to my kmemleak branch
for the nex
On Thu, Sep 22, 2011 at 01:13:01PM +0100, Jon Medhurst (Tixy) wrote:
> On Thu, 2011-09-22 at 12:57 +0100, Catalin Marinas wrote:
> > On Thu, Sep 22, 2011 at 12:06:46PM +0100, Jon Medhurst (Tixy) wrote:
> > > On Thu, 2011-09-22 at 10:48 +0100, Catalin Marinas wrote:
> > >
On Thu, Sep 22, 2011 at 12:06:46PM +0100, Jon Medhurst (Tixy) wrote:
> On Thu, 2011-09-22 at 10:48 +0100, Catalin Marinas wrote:
> > We could improve things a bit in the unwinder and assume
> > that if the fault address is the same as the .fnstart address, the
> > return valu
On 22 September 2011 08:28, Jon Medhurst (Tixy) wrote:
> On Wed, 2011-09-21 at 12:55 +0100, Russell King - ARM Linux wrote:
>> Instructions such as VFP, kprobes tracing, etc are expected fault
>> locations, and those are fairly well controlled where they can be placed.
>> With things like ftrace,
(to fit in an int), it contains an
index to another table with more bytecodes. The elements in the
unwinding table are sorted by the .fnstart address.
So I think in the above case if we don't have the .fnend/.fnstart for
Ldiv0_64 we would get all the instructions in the __do_div64 unwinding
informa
On Thu, 2011-03-24 at 18:22 +, Steve Muckle wrote:
> On ARMv7 the readl and writel macros (and readb, etc) include memory
> barriers (dmb or dsb, unless defined otherwise by the machine) due to
> CONFIG_ARM_DMA_MEM_BUFFERABLE being defined by default. Likewise the
> ioread* and iowrite* macros
On Thu, 2011-03-03 at 07:49 +, Saravana Kannan wrote:
> On 03/02/2011 12:39 AM, Russell King - ARM Linux wrote:
> > On Tue, Mar 01, 2011 at 05:23:15PM -0800, Saravana Kannan wrote:
> >> If I'm not missing some magic, this would mean that
> >> "CONFIG_ARM_DMA_MEM_BUFFERABLE" determines if readl(
On 17 December 2010 10:26, Saravana Kannan wrote:
>>> Looks like you agree with our approach. If that's the case, would you
>>> mind
>>> Acking Jeff's initial patch that this thread is based on?
>>
>> I read Catalin's reply as agreeing with me.
>
> Catalin, Can you clarify?
I'll try but I started
On 16 December 2010 06:54, Jeff Ohlstein wrote:
> --- /dev/null
> +++ b/arch/arm/mach-msm/hotplug.c
[...]
> +static inline void platform_do_lowpower(unsigned int cpu)
> +{
> + /* Just enter wfi for now. TODO: Properly shut off the cpu. */
> + for (;;) {
> + /*
> +
On 14 December 2010 04:50, Jeff Ohlstein wrote:
> --- /dev/null
> +++ b/arch/arm/mach-msm/headsmp.S
[...]
> +ENTRY(msm_secondary_startup)
> + mrc p15, 0, r0, c0, c0, 5 @ MPIDR
> + and r0, r0, #15 @ What CPU am I
> + adr r4, 1f @ address
On 13 December 2010 15:12, Catalin Marinas wrote:
> On 13 December 2010 01:20, wrote:
>> --- /dev/null
>> +++ b/arch/arm/mach-msm/hotplug.c
> [...]
>> +static inline void platform_do_lowpower(unsigned int cpu)
>> +{
>> + /* Just
On 12 December 2010 04:58, Saravana Kannan wrote:
> As you and James suggested, having the NS bit set by the secure world is
> definitely a solution that would work. But IMHO, the explicit cache
> flush/invalidate approach keeps the design simple and easy to maintain.
That is indeed an approach t
On 13 December 2010 01:20, wrote:
> --- /dev/null
> +++ b/arch/arm/mach-msm/headsmp.S
[...]
> +ENTRY(msm_secondary_startup)
> + mrc p15, 0, r0, c0, c0, 5 @ MPIDR
> + and r0, r0, #15 @ What CPU am I
> + adr r4, 1f @ address of
> +
On 13 December 2010 01:20, wrote:
> --- /dev/null
> +++ b/arch/arm/mach-msm/hotplug.c
[...]
> +static inline void platform_do_lowpower(unsigned int cpu)
> +{
> + /* Just enter wfe for now. */
> + for (;;) {
> + asm("wfe");
> + if (pen_release == cpu) {
> +
On 10 December 2010 00:58, Saravana Kannan wrote:
> Russell King - ARM Linux wrote:
>>
>> On Thu, Dec 09, 2010 at 01:23:24AM -0800, skan...@codeaurora.org wrote:
>>>
>>> Russell, Have you had a chance to look at this? Any comments? How do we
>>> move ahead?
>>
>> I had connected the other thread w
y: Russell King
Reviewed-by: Catalin Marinas
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On 5 December 2010 11:34, Russell King - ARM Linux
wrote:
> Provide gic_init() which initializes the GIC distributor and current
> CPU's GIC interface for the boot (or single) CPU.
>
> Signed-off-by: Russell King
Reviewed-by: Catalin Marinas
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On Thu, 2010-09-09 at 12:58 -0700, Daniel Walker wrote:
> Setting of these bits can cause issues on other SMP SoC's not produced
> by ARM.
>
> Signed-off-by: Daniel Walker
Acked-by: Catalin Marinas
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On Fri, 2010-08-27 at 20:53 +0100, Daniel Walker wrote:
> On Fri, 2010-08-27 at 17:49 +0100, Catalin Marinas wrote:
>
> > > So your saying it makes more sense to change the msm entry into the
> > > default entry, and make the current default into the
> > > ARM11M
On Fri, 2010-08-27 at 17:33 +0100, Daniel Walker wrote:
> On Fri, 2010-08-27 at 17:04 +0100, Catalin Marinas wrote:
> > On Fri, 2010-08-27 at 16:29 +0100, Daniel Walker wrote:
> > > On Fri, 2010-08-27 at 14:54 +0100, Catalin Marinas wrote:
> > > > On Wed, 2010-08-25
On Fri, 2010-08-27 at 16:29 +0100, Daniel Walker wrote:
> On Fri, 2010-08-27 at 14:54 +0100, Catalin Marinas wrote:
> > On Wed, 2010-08-25 at 05:57 +0100, Jeff Ohlstein wrote:
> > > From: Daniel Walker
> > >
> > > ScorpionMP does not have the SMP/nAMP and TLB
On Wed, 2010-08-25 at 05:57 +0100, Jeff Ohlstein wrote:
> From: Daniel Walker
>
> ScorpionMP does not have the SMP/nAMP and TLB ops broadcasting bits in
> ACTLR.
>
> Signed-off-by: Daniel Walker
> Signed-off-by: Jeff Ohlstein
> ---
> arch/arm/mm/proc-v7.S | 24
> 1
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