From: Simran Rai
This patch adds support for Broadcom Cygnus audio PLL and leaf
clocks
Signed-off-by: Simran Rai
Reviewed-by: Scott Branden
Signed-off-by: Ray Jui
---
drivers/clk/bcm/clk-cygnus.c | 59 ++
drivers/clk/bcm/clk-iproc-pll.c| 41 +
From: Simran Rai
Add audio clock to the existing Broadcom Cygnus clock DT
Signed-off-by: Simran Rai
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
This patch series adds support for the Cygnus audio clock based on existing
iProc clock support
This patch series is developed based on v4.4-rc1 with full tree available
on GITHUB:
repo: https://github.com/Broadcom/cygnus-linux.git
branch: cygnus-audio-clk-v1
Simran Rai (3):
Documentation: dt-b
From: Simran Rai
This patch adds audio clock device tree binding documentation to an
existing Cygnus clock DT bindings document.
Signed-off-by: Simran Rai
Reviewed-by: Ray Jui
Reviewed-by: Lori Hikichi
Reviewed-by: Scott Branden
---
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.
Remi Pommarel writes:
> Make bcm2835_clock_choose_div always round up the chosen MASH divisor so that
> the resulting average rate will not be higher than the requested one.
>
> Signed-off-by: Remi Pommarel
> ---
> drivers/clk/bcm/clk-bcm2835.c | 15 ---
> 1 file changed, 8 insertio
Remi Pommarel writes:
> Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
> parent clocks. These clocks divide the rate of a parent which can be selected
> by
> setting the proper bits in the clock control register.
>
> Previously all these parents where handled by a
Remi Pommarel writes:
> Register the pwm clock for bcm2835.
>
> Signed-off-by: Remi Pommarel
> ---
> drivers/clk/bcm/clk-bcm2835.c | 14 ++
> include/dt-bindings/clock/bcm2835.h | 3 ++-
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/bcm/clk-b
Hi,
On Wed, Nov 18, 2015 at 10:25:45AM -0800, Eric Anholt wrote:
> Remi Pommarel writes:
>
> > Make bcm2835_clock_choose_div always round up the chosen MASH divisor so
> > that
> > the resulting average rate will not be higher than the requested one.
> >
> > Signed-off-by: Remi Pommarel
> > --
On Wed, Nov 18, 2015 at 10:30:17AM -0800, Eric Anholt wrote:
[...]
> > +static int bcm2835_clock_determine_rate(struct clk_hw *hw,
> > + struct clk_rate_request *req)
> > +{
> > + struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
> > + struct clk_hw *parent, *best_parent = NU
On Wed, Nov 18, 2015 at 10:32:55AM -0800, Eric Anholt wrote:
> Remi Pommarel writes:
>
> > Register the pwm clock for bcm2835.
> >
> > Signed-off-by: Remi Pommarel
> > ---
> > drivers/clk/bcm/clk-bcm2835.c | 14 ++
> > include/dt-bindings/clock/bcm2835.h | 3 ++-
> > 2 files
On 11/17, Stephen Boyd wrote:
> +static struct clk_alpha_pll mmpll0_early = {
> + .offset = 0x0,
> + .vco_table = mmpll_p_vco,
> + .num_vco = ARRAY_SIZE(mmpll_p_vco),
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0_early",
> + .parent_names =
On 11/17, Geert Uytterhoeven wrote:
> Hi Stefan,
>
> (quoting the full driver, as it predates linux-clk)
>
> On Sun, Sep 1, 2013 at 6:40 AM, Stefan Kristiansson
> wrote:
> > This adds a simple driver with the only purpose to initialise
> > the fixed rate clock.
> > This is useful for systems tha
This patch adds support for the Sunxi thermal sensor on the Allwinner H3.
Also adds declaration of the H3 THS clock to clk-sunxi.c ignoring the
dividers as they are not continuous (clk-divider.c cannot be used as it
does not support setting an enable bit).
Should be easily extendable for the A33/A8
Hi Stephen,
On Wed, Nov 18, 2015 at 9:34 PM, Stephen Boyd wrote:
> On 11/17, Geert Uytterhoeven wrote:
>> (quoting the full driver, as it predates linux-clk)
>>
>> On Sun, Sep 1, 2013 at 6:40 AM, Stefan Kristiansson
>> wrote:
>> > This adds a simple driver with the only purpose to initialise
>>
roller with
> big endian IO accesses even though the device is little endian.
>
> Specify the endianness explicitly so that the regmap core
> properly byte swaps the accesses for us.
>
> Reported-by: Kevin Hilman
> Cc: Simon Arlott
> Cc: Mark Brown
> Signed-off-by: Steph
On 11/16, Sudip Mukherjee wrote:
> If of_clk_parent_fill() fails then we printed an error message and
> returned. But we missed freeing sp810.
>
> Signed-off-by: Sudip Mukherjee
> ---
Applied to clk-next
We don't need that error message on allocation failure either.
--
Qualcomm Innovation Cen
On 11/14, Yoshinori Sato wrote:
> read[bwl] and write[bwl] is only little-endian I/O.
> But h8300's peripheral of big-endian. So use ioread/write.
>
> And h8300 specific __raw_read/write is same of generic.
> It can remove.
>
> Signed-off-by: Daniel Lezcano
> Signed-off-by: Yoshinori Sato
> ---
Hi Shawn,
Any thoughts on that patchset? I kind of hoped that it would make it
into 4.4 since it actually fixes issues (at least 1 and 2)... That said,
I don't think it is stable material since it also breaks the device
tree...
--
Stefan
On 2015-10-17 21:05, Stefan Agner wrote:
> The Synchronous
Hello,
On Wed, 18 Nov 2015 21:51:48 +0100
Josef Gajdusek wrote:
> This patch adds support for the Sunxi thermal sensor on the Allwinner H3.
> Also adds declaration of the H3 THS clock to clk-sunxi.c ignoring the
> dividers as they are not continuous (clk-divider.c cannot be used as it
> does not
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller
IP. This series adds support for a Synopsys DesignWare MIPI DSI host
controller DRM bridge driver and a rockchip MIPI DSI specific DRM
driver.
This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel.
This panel o
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
in
On Thu, Nov 19, 2015 at 4:51 AM, Josef Gajdusek wrote:
> This patch adds support for the Sunxi thermal sensor on the Allwinner H3.
> Also adds declaration of the H3 THS clock to clk-sunxi.c ignoring the
> dividers as they are not continuous (clk-divider.c cannot be used as it
> does not support se
Hi Krzysztof,
On 11/16/2015 07:06 AM, Krzysztof Kozlowski wrote:
The ARMv8 Exynos family SoCs in Linux kernel are currently:
- Exynos5433 (controlled by ARCH_EXYNOS),
- Exynos7 (controlled by ARCH_EXYNOS7).
It duplicates Kconfig symbols unnecessarily, so consolidate them into
one ARCH_EXYNO
Hi Krzysztof,
On 11/16/2015 07:06 AM, Krzysztof Kozlowski wrote:
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
so it is built also on ARMv7. This does not bring any kind of benefit.
There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like
multi_v7 for ARMv7)
Hi Krzysztof,
Good idea, just a couple of nits inline. Other than that:
Acked-by: Tomasz Figa
2015-11-16 10:36 GMT+09:00 Krzysztof Kozlowski :
> Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
> so it is built also on ARMv7. This does not bring any kind of benefit.
> Th
Hi Krzysztof,
2015-11-16 10:36 GMT+09:00 Krzysztof Kozlowski :
> The ARMv8 Exynos family SoCs in Linux kernel are currently:
> - Exynos5433 (controlled by ARCH_EXYNOS),
> - Exynos7 (controlled by ARCH_EXYNOS7).
>
> It duplicates Kconfig symbols unnecessarily, so consolidate them into
> one ARCH_
On 19.11.2015 13:23, Tomasz Figa wrote:
> Hi Krzysztof,
>
> 2015-11-16 10:36 GMT+09:00 Krzysztof Kozlowski :
>> The ARMv8 Exynos family SoCs in Linux kernel are currently:
>> - Exynos5433 (controlled by ARCH_EXYNOS),
>> - Exynos7 (controlled by ARCH_EXYNOS7).
>>
>> It duplicates Kconfig symbols
On 19.11.2015 13:18, Tomasz Figa wrote:
> Hi Krzysztof,
>
> Good idea, just a couple of nits inline. Other than that:
>
> Acked-by: Tomasz Figa
>
> 2015-11-16 10:36 GMT+09:00 Krzysztof Kozlowski :
>> Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
>> so it is built also
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