Michael Turquette writes:
> Hi Arnd,
>
> Quoting Arnd Bergmann (2015-12-30 01:29:02)
>> It's also ok to merge the header file and binding with either the dts file
>> changes or the driver and then do the other part the following release.
>>
>> In the past, we've worked around the issue by mergin
them from specs, sorting, and adding missing ones for the clocks I meant
to expose. I'm happy to see these missing registers added, even if we
haven't exposed those clocks yet.
Reviewed-by: Eric Anholt
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Michael Turquette writes:
> On Fri, Dec 18, 2015 at 8:19 PM, Rob Herring wrote:
>> On Tue, Dec 15, 2015 at 03:35:57PM -0800, Eric Anholt wrote:
>>> These will be used for enabling UART1, SPI1, and SPI2.
>>>
>>> Signed-off-by: Eric Anholt
>>> ---
&g
Remi Pommarel writes:
> On Mon, Dec 07, 2015 at 08:09:47PM -0800, Eric Anholt wrote:
>> Stefan Wahren writes:
>>
>> > Hi Remi,
>> >
>> > Am 07.12.2015 um 19:17 schrieb Remi Pommarel:
>> >> Hi Stefan,
>> >>
>> >>
There are a pair of SPI masters and a mini UART that were last minute
additions. As a result, they didn't get integrated in the same way as
the other gates off of the VPU clock in CPRMAN.
Signed-off-by: Eric Anholt
---
v2: Make the binding cover both the IRQ and clock enable registers.
These will be used for enabling UART1, SPI1, and SPI2.
Signed-off-by: Eric Anholt
---
v2: Make the binding cover both the IRQ and clock enable registers.
.../bindings/clock/brcm,bcm2835-aux-clock.txt | 31 ++
include/dt-bindings/clock/bcm2835-aux.h| 17
These will be used for enabling UART1, SPI1, and SPI2.
Signed-off-by: Eric Anholt
---
v2: Make the binding cover both the IRQ and clock enable registers.
arch/arm/boot/dts/bcm2835.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot
Stefan Wahren writes:
> Hi Remi,
>
> Am 07.12.2015 um 19:17 schrieb Remi Pommarel:
>> Hi Stefan,
>>
>> On Sun, Dec 06, 2015 at 10:16:25PM +0100, Stefan Wahren wrote:
>>> Hi Remi,
>>>
>>> please send this patch to devicet...@vger.kernel.org.
>>
>> Ok, just to be sure I understand the process here.
> allowing them to select the one to use.
I see, you use the new flag now in this patch. I take back the comment
on the previous patch.
Patches 1-3 are:
Reviewed-by: Eric Anholt
and I think they're ready to go in the clock tree, even while the DT for
setting up the bcm2835-pwm driver
lock->cprman;
> const struct bcm2835_clock_data *data = clock->data;
> - u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
> + u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
I think you meant ", true" on one of these. With that fixed,
Reviewed-by: Eric Anholt
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Remi Pommarel writes:
> On Thu, Dec 03, 2015 at 04:37:07PM -0800, Eric Anholt wrote:
>> Remi Pommarel writes:
>>
>> > On Wed, Nov 18, 2015 at 10:30:17AM -0800, Eric Anholt wrote:
>> >
>> > [...]
>> >
>> >&g
Remi Pommarel writes:
> On Wed, Nov 18, 2015 at 10:30:17AM -0800, Eric Anholt wrote:
>
> [...]
>
>> > +static int bcm2835_clock_determine_rate(struct clk_hw *hw,
>> > + struct clk_rate_request *req)
>> > +{
>> > + struct bcm2835_clock *c
Remi Pommarel writes:
> Hi,
>
> On Wed, Nov 18, 2015 at 10:25:45AM -0800, Eric Anholt wrote:
>> Remi Pommarel writes:
>>
>> > Make bcm2835_clock_choose_div always round up the chosen MASH divisor so
>> > that
>> > the resulting averag
--git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 2b01a53..db378f3 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -39,6 +39,7 @@
>
> #include
> #include
> +#include
Stray new #include? With that drop
eq->rate) {
> + best_parent = parent;
> + best_prate = prate;
> + best_rate = rate;
> + }
> + }
> +
> + if (!best_parent)
> + return -EINVAL;
> +
> + req->best_parent_hw = best_parent;
> + req->best_parent_rate = best_prate;
I think you're supposed to req->rate = best_rate, here, too. With these
two fixes,
Reviewed-by: Eric Anholt
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Remi Pommarel writes:
> Make bcm2835_clock_choose_div always round up the chosen MASH divisor so that
> the resulting average rate will not be higher than the requested one.
>
> Signed-off-by: Remi Pommarel
> ---
> drivers/clk/bcm/clk-bcm2835.c | 15 ---
> 1 file changed, 8 insertio
Remi Pommarel writes:
> Hi,
>
> On Wed, Nov 04, 2015 at 06:03:31PM -0800, Eric Anholt wrote:
>
> [...]
>
>>
>> It looks like you've dropped the use of the divisor off of the PLL
>> channel when setting a rate. That seems bad for all the other clocks in
Remi Pommarel writes:
> Register the pwm clock for bcm2835.
> This patch also adds the ability to set a clock default rate.
I don't think we should be setting a default clock rate. That should be
up to the thing that uses the clock. If we need a standard rate set on
all Raspberry Pis, other th
Remi Pommarel writes:
> Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
> parents. These clocks divide the rate of one parent which can be selected by
> setting the proper bits in their clock control register.
>
> Previously all these parents where handled by a mux c
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
Tested-by: Martin Sperl
---
v2: Fix o
Stephen Boyd writes:
> Please drop the full-stop from your subject lines.
>
> On 10/08, Eric Anholt wrote:
>> This adds support for enabling, disabling, and setting the rate of the
>> audio domain clocks. It will be necessary for setting the pixel clock
>> for HDMI i
Stephen Boyd writes:
> On 10/06, Eric Anholt wrote:
>> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
>> index dd295e4..b4d4421 100644
>> --- a/drivers/clk/bcm/clk-bcm2835.c
>> +++ b/drivers/clk/bcm/clk-bcm2835.c
>> @@ -17,10 +17,
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
Tested-by: Martin Sperl
---
v2: Fix o
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
Tested-by: Martin Sperl
---
v2: Fix o
Stefan Wahren writes:
> Hi Eric,
>
> Am 02.10.2015 um 21:54 schrieb Eric Anholt:
>> This adds support for enabling, disabling, and setting the rate of the
>> audio domain clocks. It will be necessary for setting the pixel clock
>> for HDMI in the VC4 driver and le
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
Tested-by: Martin Sperl
---
This is the
Stephen Boyd writes:
> On 09/28, Eric Anholt wrote:
>> +
>> +static const char *bcm2835_clock_per_parents[] = {
>> +static const char *bcm2835_clock_vpu_parents[] = {
>> +static const char *bcm2835_clock_osc_parents[] = {
>
> Can these parent arrays be const char
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
Tested-by: Martin Sperl
---
v2: Fix o
but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: E
Previously we've only supported a few fixed clocks based on
assumptions about how the firmware sets up the clocks, but this
binding will let us control the actual (audio power domain) clock
manager.
Signed-off-by: Eric Anholt
Acked-by: Stephen Warren
---
.../bindings/clock/brcm,bc
clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: Eric Anholt
Acked-by: Stephen Warren
---
drivers/clk/Makefile| 1 -
drivers/clk/bcm/Makefile| 1 +
drivers/clk/{ => bcm}/clk-b
Stephen Warren writes:
> On 09/10/2015 02:58 PM, Eric Anholt wrote:
>> This adds support for enabling, disabling, and setting the rate of the
>> audio domain clocks. It will be necessary for setting the pixel clock
>> for HDMI in the VC4 driver and let us write a cpu
Stephen Warren writes:
> On 09/10/2015 03:22 PM, Eric Anholt wrote:
>> These will be used for enabling UART1, SPI1, and SPI2.
>
>> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
>
>> +aux_clocks: aux-clocks@0x7e215004 {
>>
This is a followup to the main audio domain clocks series I just
posted. There's a clock gate register controlling the clocks for a
few extra peripherals, and Martin Sperl has been working on the SPI
driver for 2/3 of them (the other is a simple UART). This gives those
drivers the clock gate enab
There are a pair of SPI masters and a mini UART that were last minute
additions. As a result, they didn't get integrated in the same way as
the other gates off of the VPU clock in CPRMAN.
Signed-off-by: Eric Anholt
---
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm2835-
These will be used for enabling UART1, SPI1, and SPI2.
Signed-off-by: Eric Anholt
---
arch/arm/boot/dts/bcm2835.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index a6a55b7..7c37956 100644
--- a/arch/arm/boot/dts
These will be used for enabling UART1, SPI1, and SPI2.
Signed-off-by: Eric Anholt
---
.../bindings/clock/brcm,bcm2835-aux-clock.txt | 30 ++
include/dt-bindings/clock/bcm2835-aux.h| 17
2 files changed, 47 insertions(+)
create mode 100644
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
---
v2: Fix onecell->clks[] allocation
Previously we've only supported a few fixed clocks based on
assumptions about how the firmware sets up the clocks, but this
binding will let us control the actual (audio power domain) clock
manager.
Signed-off-by: Eric Anholt
---
.../bindings/clock/brcm,bcm2835-cprman.txt
but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed
clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: Eric Anholt
---
drivers/clk/Makefile| 1 -
drivers/clk/bcm/Makefile| 1 +
drivers/clk/{ => bcm}/clk-bcm2835.c | 0
3 files ch
Eric Anholt writes:
> This adds support for enabling, disabling, and setting the rate of the
> audio domain clocks. It will be necessary for setting the pixel clock
> for HDMI in the VC4 driver and let us write a cpufreq driver. It will
> also improve compatibility with user ch
e() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt
---
drivers/clk
Previously we've only supported a few fixed clocks based on
assumptions about how the firmware sets up the clocks, but this
binding will let us control the actual (audio power domain) clock
manager.
Signed-off-by: Eric Anholt
---
.../bindings/clock/brcm,bcm2835-cprman.txt
clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: Eric Anholt
---
drivers/clk/Makefile | 1 -
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm2835.c
After my last firmware clocks posting, Gordon at Raspberry Pi pointed
that you can, in fact, touch the clocks from the ARM side. This is
the driver that resulted from that. With debug printfs at boot the
clock frequencies from .recalc_rate() are looking good, a few are
definitely corrected compar
but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed
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