[PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac

We need to add HCLK_MAC id explicitly because that it is referred by hclk in the emac driver. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |2 +- include/dt-bindings/clock/rk3036-cru.h |1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers

[PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error

Due to a copy-paste error the uart1 and uart2 clock div set incorrect, we should to fix it. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip

[PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock

There is only support rmii in the RK3036, so we should use the correct ext clock name. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c

[PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock

Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a

[PATCH v2 0/5] fix some clock configuration for the RK3036 platform

Hi: In the development work, we found that some of the previous incorrect clock configuration on the RK3036 platform, we should fix them. Xing Zheng (5): clk: rockchip: rk3036: fix the FLAGs for clock mux clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the div

[PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux

The DFLAGS are used for the clock dividers, the CLKSEL_CON flags of COMPOSITE_NODIV type should be MFLAGS. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b

Re: [RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

Hi Heiko, On 2016年01月02日 10:34, Xing Zheng wrote: > Hi Heiko, > Thank you for your patch, I will apply and test it later. > > Thanks. > >> 在 2016年1月2日，06:10，Heiko Stübner 写道： >> >> Hi Xing, >> >> Am Dienstag, 29. Dezember 2015, 10:34:09 schrie

Re: [RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

Hi Heiko, Thank you for your patch, I will apply and test it later. Thanks. > 在 2016年1月2日，06:10，Heiko Stübner 写道： > > Hi Xing, > > Am Dienstag, 29. Dezember 2015, 10:34:09 schrieb Xing Zheng: >> On 2015年12月29日 09:59, Yakir Yang wrote: >>> On 12/28/2015

Re: [RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

On 2015年12月29日 09:59, Yakir Yang wrote: Hi Heiko, On 12/28/2015 08:41 PM, Heiko Stübner wrote: Hi, Am Montag, 28. Dezember 2015, 17:03:53 schrieb Xing Zheng: Due to referred old version TRM, there is incorrect emac clock node, we should fix it. The SEL_21_9 is the parent of SEL_21_4. In the

[RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

provide the accurate rate for mac_ref which need to 50MHz probability, we should let it under the APLL and are able to set the freq which integer multiples of 50MHz, so we add these emac node for reference. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c | 11

[RESEND PATCH v1 1/4] clk: rockchip: rk3036: fix the FLAGs for clock mux

The DFLAGS are used for the clock dividers, the CLKSEL_CON flags of COMPOSITE_NODIV type should be MFLAGS. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b

[RESEND PATCH v1 0/4] fix some clock configuration for the RK3036 platform

Hi: In the development work, we found that some of the previous incorrect clock configuration on the RK3036 platform, we should fix them. Xing Zheng (4): clk: rockchip: rk3036: fix the FLAGs for clock mux clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: rename emac

[RESEND PATCH v1 3/4] clk: rockchip: rk3036: rename emac ext source clock

There is only support rmii in the RK3036, so we should use the correct ext clock name. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c

[RESEND PATCH v1 2/4] clk: rockchip: rk3036: fix uarts clock error

Due to a copy-paste error the uart1 and uart2 clock div set incorrect, we should to fix it. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip

[PATCH 2/2] clk: rockchip: rk3036: fix and add node id for emac clock

the accurate rate for mac_ref which need to 50MHz probability, we should let it under the APLL and are able to set the freq which integer multiples of 50MHz, so we add these emac node for reference. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c | 11 ++- include

[PATCH 1/2] clk: rockchip: rk3036: rename emac ext source clock

There is only support rmii in the RK3036, so we should use the correct ext clock name. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3036.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c

Re: [PATCH v7 0/6] Build and support rk3036 SoC platform

OK, Thanks Heiko. :-) On 2015年11月24日 08:03, Heiko Stübner wrote: Hi Xing Zheng, Am Donnerstag, 5. November 2015, 15:33:54 schrieb Xing Zheng: Hi, We need to support rk3036 soc platform via upstream, there are some primary parts for the initial release of minimum system: dts, clk-pll, smp

[PATCH v7 4/6] clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v7: None drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-rk3036.c | 478 + drivers/clk/rockchip/clk.h

[PATCH v7 3/6] clk: rockchip: add new pll-type for rk3036 and similar socs

The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Ch

[PATCH v7 0/6] Build and support rk3036 SoC platform

ller for rk3036 3) clk: rockchip: add new pll-type for rk3036 and similar socs 2) clk: rockchip: add dt-binding header for rk3036 1) dt-bindings: add documentation of rk3036 clock controller Changes in v7: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Xing Zheng (6): dt-bindings:

[PATCH v6 4/8] clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v6: None drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-rk3036.c | 478 + 2 files changed, 479 insertions

[PATCH v6 3/8] clk: rockchip: add new pll-type for rk3036 and similar socs

The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Ch

[PATCH v6 0/8] Build and support rk3036 SoC platform

6 and similar socs 2) clk: rockchip: add dt-binding header for rk3036 1) dt-bindings: add documentation of rk3036 clock controller Changes in v6: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Heiko Stuebner (1): ARM: rockchip: add support smp for rk3036 Xing Zheng (7): dt-bindings: add docu

[PATCH v5 0/8] Build and support rk3036 SoC platform

mentation of rk3036 clock controller Changes in v5: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Heiko Stuebner (1): ARM: rockchip: add support smp for rk3036 Xing Zheng (7): dt-bindings: add documentation of rk3036 clock controller clk: rockchip: add dt-binding header for rk3036

[PATCH v5 4/8] clk: rockchip: add new pll-type for rk3036 and similar socs

The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Ch

[PATCH v5 3/8] clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v5: None drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-rk3036.c | 500 + drivers/clk/rockchip/clk.h

[PATCH v4 4/8] clk: rockchip: add new pll-type for rk3036 and similar socs

The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Ch

[PATCH v4 0/8] Build and support rk3036 SoC platform

) ARM: dts: rockchip: add core rk3036 dts 4) clk: rockchip: add new pll-type for rk3036 and similar socs 3) clk: rockchip: add clock controller for rk3036 2) clk: rockchip: add dt-binding header for rk3036 1) dt-bindings: add documentation of rk3036 clock controller Changes in v4: Signed-off-by: Xin

[PATCH v4 3/8] clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v4: None drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-rk3036.c | 500 + drivers/clk/rockchip/clk.h

Re: [PATCH 1/3] clk: add flag for clocks that need to be enabled on rate changes

for that clock type :-) . Xing Zheng now also independently stumbled upon this issue with his rk3036 work. And came to the same conclusion that the gate must be enabled as well as the downstream mux be set to the fractional divider for it to actually accept a new setting. Yes, I discussed such prob

[PATCH v3 5/8] clk: rockchip: add new clock type and controller for rk3036

The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Ch

[PATCH v3 3/8] clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v3: None drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-rk3036.c | 500 drivers/clk/rockchip/clk.h

[PATCH v3 0/8] Build and support rk3036 SoC platform

tion of rk3036 clock controller 3) clk: rockchip: add clock controller for rk3036 2) clk: rockchip: add dt-binding header for rk3036 1) ARM: dts: rockchip: add core rk3036 dts Changes in v3: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Xing Zheng (8): ARM: dts: rockchip: add core rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

On 2015年09月24日 11:04, Xing Zheng wrote: #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)\ @@ -95,12 +106,31 @@ enum rockchip_pll_type { .nb = _nb,\ } +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,\ +_postdiv2, _dsmpd, _frac

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

On 2015年09月17日 17:47, Heiko Stübner wrote: Hi, Am Donnerstag, 17. September 2015, 16:28:54 schrieb Xing Zheng: Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng missing a dt-bindings document in a separate patch. See "dt-bindings: add documentation of r

Re: [PATCH v1 3/3] clk: rockchip: add clock controller for rk3036

On 2015年08月28日 17:54, Heiko Stuebner wrote: Hi, Am Freitag, 28. August 2015, 13:46:48 schrieb Xing Zheng: Add the clock tree definition for the new rk3036 SoC, but there are some issues to be fixed: 1. soc will crash if gpll run rate_change_remuxed 2. rk3036_clk_suspend and rk3036_clk_resume

[PATCH v2 0/9] Build and support rk3036 SoC platform

controller for rk3036 2) clk: rockchip: add dt-binding header for rk3036 1) ARM: dts: rockchip: add core rk3036 dts Changes in v2: Signed-off-by: Xing Zheng Xing Zheng (9): ARM: dts: rockchip: add core rk3036 dts clk: rockchip: add dt-binding header for rk3036 clk: rockchip: add clock

[PATCH v2 4/9] clk: rockchip: add new clock type and controller for rk3036

The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng --- Changes in v2: None driver

[PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng --- Changes in v2: None drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-rk3036.c | 504 + drivers/clk/rockchip/clk.h| 30 +++ 3 files changed