SEC ERA has to be retrieved by reading the fsl,sec-era property
from the device tree. This property is updated/filled in by
u-boot.
Change-Id: Ie1620354a0cf2cac5cd2c72bd5f2449f55858378
Signed-off-by: Alex Porosanu alexandru.poros...@freescale.com
---
drivers/crypto/caam/ctrl.c | 36
On 2/6/2014 10:27 AM, Alex Porosanu wrote:
SEC ERA has to be retrieved by reading the fsl,sec-era property
from the device tree. This property is updated/filled in by
u-boot.
Change-Id: Ie1620354a0cf2cac5cd2c72bd5f2449f55858378
Change-Id should be dropped.
Signed-off-by: Alex Porosanu
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/arm64/Makefile | 1 +
arch/arm64/crypto/Makefile| 13 ++
arch/arm64/crypto/aes-ce-cipher.c | 257 ++
crypto/Kconfig| 6 +
4 files changed, 277
Many ciphers perform better when allowed to operate on data sizes that are
larger than the natural block size of the algorithm.
This patch adds a struct member .cia_interleave which holds the preferred
number of blocks processed in a single invocation. The invocations themselves
should occur
My apologies if this has been discussed/debated before on linux-crypto.
When working on accelerated crypto for ARM and arm64, I noticed that many of
the existing accelerated implementations for other architectures duplicate much
of the chaining modes, not because they can be accelerated
As CBC decryption can be executed in parallel, take the cipher alg's
preferred interleave into account when decrypting data.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
crypto/cbc.c | 109 ---
1 file changed, 82
Hi Naveen,
On 29.01.2014 10:20, Naveen Krishna Chatradhi wrote:
This patch adds device tree support to the s5p-sss.c crypto driver.
Also, Documentation under devicetree/bindings added.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu herb...@gondor.apana.org.au
CC: David
Hi Naveen,
On 29.01.2014 10:21, Naveen Krishna Chatradhi wrote:
This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available
Hi Naveen,
On 29.01.2014 10:22, Naveen Krishna Chatradhi wrote:
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.
Signed-off-by:
Hi Naveen,
On 29.01.2014 10:24, Naveen Krishna Chatradhi wrote:
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
TO: linux-samsung-...@vger.kernel.org
TO: Tomasz Figa t.f...@samsung.com
CC: Kukjin
On Thu, Feb 06, 2014 at 01:25:01PM +0100, Ard Biesheuvel wrote:
My apologies if this has been discussed/debated before on linux-crypto.
When working on accelerated crypto for ARM and arm64, I noticed that many of
the existing accelerated implementations for other architectures duplicate
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource 0 and hash interrupt as 1.
reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung
This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
Reviewed-by:
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
Reviewed-by: Tomasz Figa
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
TO: linux-samsung-...@vger.kernel.org
CC: Kukjin Kim kgene@samsung.com
CC: linux-crypto@vger.kernel.org
This patch adds code to validate iv buffer before trying to
memcpy the contents
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
changes since v5:
None
drivers/crypto/s5p-sss.c |3 ++-
1 file changed, 2 insertions(+), 1
This patch set adds use of clk_prepare/clk_unprepare as
required by generic clock framework.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
changes since v5:
None
drivers/crypto/s5p-sss.c | 10 +++---
1 file changed, 7
From: Naveen Krishna Ch ch.nav...@samsung.com
Currently, the driver enqueues a request only if the busy bit is
false. And every request initiates a dequeue. If 2 requests arrive
simultaneously, only one of them will be dequeued.
To avoid this senario, we will enqueue the next request
On 7 February 2014 03:23, Herbert Xu herb...@gondor.apana.org.au wrote:
On Thu, Feb 06, 2014 at 01:25:01PM +0100, Ard Biesheuvel wrote:
My apologies if this has been discussed/debated before on linux-crypto.
When working on accelerated crypto for ARM and arm64, I noticed that many of
the
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