Dan Streetman ddstr...@ieee.org wrote:
I see the algif_hash and algif_blkcipher implementations to allow
userspace AF_ALG socket access to kernel blkcipher and hash
algorithms, but has anyone done a algif_compression to allow userspace
access to compression algs? I'm asking specifically wrt
Hi,
The following patch set implements support for Qualcomm
crypto hardware accelerator driver. It registers itself
to the crypto subsystem and adds the following operations
for encryption/decription - AES with ECB CBC CTR XTS modes,
DES with ECB CBC modes, and 3DES ECB CBC modes.
For hashing and
This adds core driver files. The core part is implementing a
platform driver probe and remove callbaks, the probe enables
clocks, checks crypto version, initialize and request dma
channels, create done tasklet and work queue and finally
register the algorithms into crypto subsystem.
This adds dmaengine and sg-list helper functions used by
other parts of the crypto driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/dma.c | 201 +++
drivers/crypto/qce/dma.h | 57 ++
2 files changed, 258
Here are all register addresses and bit/masks used by the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/regs-v5.h | 327 +++
1 file changed, 327 insertions(+)
create mode 100644 drivers/crypto/qce/regs-v5.h
diff
Here is the implementation of AES, DES and 3DES crypto API
callbacks, the crypto register alg function, the async request
handler and its dma done callback function.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/ablkcipher.c | 397
Here is the implementation and registration of ahash crypto type.
It includes sha1, sha256, hmac(sha1) and hmac(sha256).
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/sha.c | 595 +++
drivers/crypto/qce/sha.h | 74 ++
Here are functions used to setup/prepare hardware registers for
all algorithms supported by the crypto block. It also exports
few helper functions needed by algorithms:
- to check hardware status
- to start crypto hardware
- to translate data stream to big endian form
Adds Makefile needed to build the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/Makefile | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 drivers/crypto/qce/Makefile
diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile
new
Modify crypto Kconfig and Makefile in order to build the qce
driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/Kconfig | 10 ++
drivers/crypto/Makefile | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
On Apr 3, 2014, at 11:17 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Here are all register addresses and bit/masks used by the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/regs-v5.h | 327 +++
1 file
Hi,
On 04/03/2014 07:24 PM, Kumar Gala wrote:
On Apr 3, 2014, at 11:17 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Here are all register addresses and bit/masks used by the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/regs-v5.h | 327
On Apr 3, 2014, at 11:33 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Hi,
On 04/03/2014 07:24 PM, Kumar Gala wrote:
On Apr 3, 2014, at 11:17 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Here are all register addresses and bit/masks used by the driver.
Signed-off-by:
On Thu, Apr 3, 2014 at 8:41 AM, Herbert Xu herb...@gondor.apana.org.au wrote:
Dan Streetman ddstr...@ieee.org wrote:
I see the algif_hash and algif_blkcipher implementations to allow
userspace AF_ALG socket access to kernel blkcipher and hash
algorithms, but has anyone done a algif_compression
Hey Stanimir-
Just a few comments/questions from a quick scan of your patchset:
On Thu, Apr 03, 2014 at 07:17:58PM +0300, Stanimir Varbanov wrote:
[..]
+++ b/drivers/crypto/qce/core.c
[..]
+
+static struct qce_algo_ops qce_ops[] = {
+ {
+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
Nitworthy comments :).
On Thu, Apr 03, 2014 at 07:18:00PM +0300, Stanimir Varbanov wrote:
[..]
+++ b/drivers/crypto/qce/dma.c
[..]
+int qce_dma_request(struct device *dev, struct qce_dma_data *dma)
+{
+ unsigned int memsize;
+ void *va;
+ int ret;
+
+ dma-txchan =
On Thu, Apr 03, 2014 at 06:18:00PM +0200, Stanimir Varbanov wrote:
This adds dmaengine and sg-list helper functions used by
other parts of the crypto driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/dma.c | 201
On Thu, Apr 03, 2014 at 06:17:58PM +0200, Stanimir Varbanov wrote:
This adds core driver files. The core part is implementing a
platform driver probe and remove callbaks, the probe enables
clocks, checks crypto version, initialize and request dma
channels, create done tasklet and work queue
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