Hi Linus:
Here is the crypto update for 3.16:
* Added test vectors for SHA/AES-CCM/DES-CBC/3DES-CBC.
* Fixed a number of error-path memory leaks in tcrypt.
* Fixed error-path memory leak in caam.
* Removed unnecessary global mutex from mxs-dcp.
* Added ahash walk interface that can actually be
Herbert:
Did anyone report problem on the area of authen(hmac(sha1), cbc(aes)) fallback,
since linux 3-10?
I am working on android linux 3-10.
Our hardware does not support aes 192.
I am following the example from picoxcell_crypto.c. In the cra_init, driver
does the following to allocate
a
This patch provides the documentation of the device bindings
for the AMD Cryptographic Coprocessor driver.
Signed-off-by: Tom Lendacky thomas.lenda...@amd.com
---
.../devicetree/bindings/crypto/amd-ccp.txt | 16
1 file changed, 16 insertions(+)
create mode 100644
The following series implements support for the CCP as a platform
driver on ARM64.
This patch series is based on the cryptodev-2.6 kernel tree.
---
Tom Lendacky (3):
crypto: ccp - Modify PCI support in prep for arm64 support
crypto: ccp - CCP device bindings documentation
Add support for the CCP on arm64 as a platform device.
Signed-off-by: Tom Lendacky thomas.lenda...@amd.com
---
drivers/crypto/Kconfig|2
drivers/crypto/ccp/Makefile |5 +
drivers/crypto/ccp/ccp-dev.c | 34 ++
drivers/crypto/ccp/ccp-dev.h |7 +
Modify the PCI device support in prep for supporting the
CCP as a platform device for arm64.
Signed-off-by: Tom Lendacky thomas.lenda...@amd.com
---
drivers/crypto/ccp/ccp-dev.h |3 +--
drivers/crypto/ccp/ccp-pci.c | 39 ++-
2 files changed, 15
This patch adds FW interface structure definitions.
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/icp_qat_fw.h | 316
Hi,
This patchset adds support for Intel(R) QuickAssist Technology (QAT) and
DH895xCC hardware accelerator.
First four patches add a common infractructure that will be used by all QAT
devices.
Patch five and six add a firmware loader module that is used to load the
microcode to the acceleration
This patch adds microcode part of the firmware loader.
v4 - splits FW loader part into two smaller patches.
Acked-by: Bo Cui bo@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Karen Xiang karen.xi...@intel.com
Signed-off-by: Pingchaox Yang
This patch adds DH895xCC hardware specific code.
It hooks to the common infrastructure and provides acceleration for crypto
algorithms.
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Update to makefiles etc.
Don't update the firmware/Makefile yet since there is no FW binary in
the crypto repo yet. This will be added later.
v3 - removed change to ./firmware/Makefile
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
On Thursday, June 05, 2014 at 03:11:33 AM, Amos Kong wrote:
In crypto/xor.c: calibrate_xor_blocks(), we allocated total 4 pages to
do xor speed testing, the BENCH_SIZE is 1 page, and we skipped 2 pages
when we set b2.
It seems that total 2 pages are enough without skipping 2 pages.
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