The driver is compatible with SEC version 4.0, which was missing from
device tree resulting that the caam driver doesn't gets probed. Since
SEC is backward compatible with older versions, so this patch adds those
missing versions in c29x device tree.
Signed-off-by: Nitesh Narayan Lal
In the current setup debug file system enables us to debug the operational
details for only one CAAM. This patch adds the support for debugging multiple
CAAM's.
Signed-off-by: Nitesh Narayan Lal b44...@freescale.com
Signed-off-by: Vakul Garg b16...@freescale.com
---
drivers/crypto/caam/ctrl.c |
Hello
I am writing the PRNG driver for the Allwinner Security System SoC A20.
I didn't know how to test it, so I have found that char/hw_random/exynos-rng.c
exposes a PRNG via the hwrng interfaces.
So I have written a HWRNG driver that use the SS PRNG via the crypto API
The patch corrects the security strength of the HMAC-SHA1 DRBG to 128
bits. This strength defines the size of the seed required for the DRBG.
Thus, the patch lowers the seeding requirement from 256 bits to 128 bits
for HMAC-SHA1.
Signed-off-by: Stephan Mueller smuel...@chronox.de
---
For the CTR DRBG, the drbg_state-scratchpad temp buffer (i.e. the
memory location immediately before the drbg_state-tfm variable
is the buffer that the BCC function operates on. BCC operates
blockwise. Making the temp buffer drbg_statelen(drbg) in size is
sufficient when the DRBG state length is a
The current locking approach of the DRBG tries to keep the protected
code paths very minimal. It is therefore possible that two threads query
one DRBG instance at the same time. When thread A requests random
numbers, a shadow copy of the DRBG state is created upon which the
request for A is
When the DRBG is initialized, the core is looked up using the DRBG name.
The name that can be used for the lookup is registered in
cra_driver_name. The cra_name value contains stdrng.
Thus, the lookup code must use crypto_tfm_alg_driver_name to obtain the
precise DRBG name and select the correct
Hi,
the following fixes cover comments from code reviewers. The patch set
is an addition to the patch set offered several days ago [1].
[1] https://lkml.org/lkml/2014/6/28/497
Stephan Mueller (4):
DRBG: Select correct DRBG core for stdrng
DRBG: Mix a time stamp into DRBG state
DRBG: fix
Hi,
On Mon, Jun 30, 2014 at 07:38:46PM +0300, Jussi Kivilinna wrote:
Common SHA-1 structures are defined in crypto/sha.h for code sharing.
This patch changes SHA-1/ARM glue code to use these structures.
I find it worth noting that this patch also fixes mv_cesa if sha1-arm is
also enabled.
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -55,7 +55,7 @@
* cpu_arm926_proc_init()
*/
ENTRY(cpu_arm926_proc_init)
- mov pc, lr
+ ret lr
/*
* cpu_arm926_proc_fin()
@@ -65,7 +65,7 @@ ENTRY(cpu_arm926_proc_fin)
bic r0, r0, #0x1000
Russell King rmk+ker...@arm.linux.org.uk writes:
ARMv6 and greater introduced a new instruction (bx) which can be used
to return from function calls. Recent CPUs perform better when the
bx lr instruction is used rather than the mov pc, lr instruction,
and this sequence is strongly
On Tue, Jul 01, 2014 at 05:42:42PM +0100, Måns Rullgård wrote:
Russell King rmk+ker...@arm.linux.org.uk writes:
ARMv6 and greater introduced a new instruction (bx) which can be used
to return from function calls. Recent CPUs perform better when the
bx lr instruction is used rather than
Russell King - ARM Linux li...@arm.linux.org.uk writes:
On Tue, Jul 01, 2014 at 05:42:42PM +0100, Måns Rullgård wrote:
Russell King rmk+ker...@arm.linux.org.uk writes:
ARMv6 and greater introduced a new instruction (bx) which can be used
to return from function calls. Recent CPUs perform
Hi Mans,
On Tue, Jul 01, 2014 at 06:24:43PM +0100, Måns Rullgård wrote:
Russell King - ARM Linux li...@arm.linux.org.uk writes:
As you point out, bx lr /may/ be treated specially (I've actually been
Most, if not all, Cortex-A cores do this according the public TRMs.
They also do the same
On 07/01/2014 10:19 AM, Russell King wrote:
ARMv6 and greater introduced a new instruction (bx) which can be used
to return from function calls. Recent CPUs perform better when the
bx lr instruction is used rather than the mov pc, lr instruction,
and this sequence is strongly recommended to
Will Deacon will.dea...@arm.com writes:
Hi Mans,
On Tue, Jul 01, 2014 at 06:24:43PM +0100, Måns Rullgård wrote:
Russell King - ARM Linux li...@arm.linux.org.uk writes:
As you point out, bx lr /may/ be treated specially (I've actually been
Most, if not all, Cortex-A cores do this
Depending on the IMA policy, it might require to measure huge amount of files.
It may be very important to speedup hash calculation or to reduce (bettery)
energy required to do it. Currently IMA uses synchronous hash API (shash)
which is CPU based. CPU based hash calculation is very CPU intensive
Asynchronous hash API allows initiate hash calculation and perform
other tasks while hash is calculated.
This patch introduces usage of double buffering for simultaneous
hashing and reading of the next chunk of data from the storage.
Signed-off-by: Dmitry Kasatkin d.kasat...@samsung.com
---
Use of multiple-page collect buffers reduces:
1) the number of block IO requests
2) the number of asynchronous hash update requests
Second is important for HW accelerated hashing, because significant
amount of time is spent for preparation of hash update operation,
which includes configuring
Async hash API allows to use HW acceleration for hash calculation.
It may give significant performance gain or/and reduce power consumption,
which might be very beneficial for battery powered devices.
This patch introduces hash calculation using ahash API.
ahash performance depends on data size
Russell King rmk+ker...@arm.linux.org.uk writes:
ARMv6 and greater introduced a new instruction (bx) which can be used
to return from function calls. Recent CPUs perform better when the
bx lr instruction is used rather than the mov pc, lr instruction,
and this sequence is strongly
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