[PATCH v1 3/3] SHA1 for PPC/SPE - kernel config
Integrate the module into the kernel config tree.
Signed-off-by: Markus Stockhausen stockhau...@collogia.de
diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile
index 1698fb9..d400bf9 100644
--- a/arch/powerpc/crypto/Makefile
[PATCH v1 0/3] SHA1 for PPC/SPE
The following patches add support for SIMD accelerated SHA1
calculation on PPC processors with SPE instruction set. The
implementation takes care of the following constraints:
- independant of processor endianess
- save SPE registers for interrupt context
[PATCH v1 2/3] SHA1 for PPC/SPE - glue
Glue code for crypto infrastructure. Call the assembler
code where required. Disable preemption during calculation
and enable SPE instructions in the kernel prior to the
call. Avoid to disable preemption for too long.
Take a little care about small input
[PATCH v1 1/3] SHA1 for PPC/SPE - assembler
This is the assembler code for SHA1 implementation with
the SIMD SPE instruction set. With the enhanced instruction
set we can operate on 2 32 bit words in parallel. That helps
reducing the time to calculate W16-W79. For increasing
performance even
On Tuesday 24 February 2015 18:25:12 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150218 16:03]:
On Wednesday 18 February 2015 22:02:30 Pali Rohár wrote:
On Wednesday 18 February 2015 13:21:03 Pali Rohár wrote:
Hello,
I tried to test OMAP AES driver on Nokia N900 with
* Pali Rohár pali.ro...@gmail.com [150218 16:03]:
On Wednesday 18 February 2015 22:02:30 Pali Rohár wrote:
On Wednesday 18 February 2015 13:21:03 Pali Rohár wrote:
Hello,
I tried to test OMAP AES driver on Nokia N900 with special
Nokia bootloader which enable L3 firewall for OMAP
On Tuesday 24 February 2015 18:37:34 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150224 09:42]:
On Tuesday 24 February 2015 18:25:12 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150218 16:03]:
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++
On 2/20/2015 6:21 PM, Martin Hicks wrote:
I was running into situations where the hardware FIFO was filling up, and
the code was returning EAGAIN to dm-crypt and just dropping the submitted
crypto request.
This adds support in talitos for a software backlog queue. When requests
can't be
* Pali Rohár pali.ro...@gmail.com [150224 09:42]:
On Tuesday 24 February 2015 18:25:12 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150218 16:03]:
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3938,8 +3938,9 @@ int
* Pali Rohár pali.ro...@gmail.com [150224 09:52]:
On Tuesday 24 February 2015 18:37:34 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150224 09:42]:
On Tuesday 24 February 2015 18:25:12 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150218 16:03]:
---
Hi ,
I am working on understanding crypt drivers in implemented in
asynchronous mode.I am little ambiguous regarding following
scenario,Please
can some help me with this.
#1: If two or more applications will send their requests (may be
different seesions) to crypto Hardware (may be scheduler
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