Entry for Inline TLS as another driver dependent on cxgb4 and chcr
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/Kconfig| 11 +++
drivers/crypto/chelsio/Makefile | 1 +
drivers/crypto/chelsio/chtls/Makefile | 4
3 files changed, 16 insertions(+)
create mode 1
Program the tx and rx key on chip.
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chtls/chtls_hw.c | 394
1 file changed, 394 insertions(+)
create mode 100644 drivers/crypto/chelsio/chtls/chtls_hw.c
diff --git a/drivers/crypto/chelsio/chtls/chtls_hw.c
b/
Register chtls as Inline TLS driver, chtls is ULD to cxgb4.
Setsockopt to program (tx/rx) keys on chip. Support AES GCM
of key size 128. Support both Inline Rx and Tx.
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chtls/chtls_main.c | 600 ++
include/uapi/linux
TLS handler for record transmit and receive.
Create Inline TLS work request and post to FW.
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chtls/chtls_io.c | 1867 +++
1 file changed, 1867 insertions(+)
create mode 100644 drivers/crypto/chelsio/chtls/chtls_io.c
CPL handlers for TLS session, record transmit and receive.
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chtls/chtls_cm.c | 2041 +++
net/ipv4/tcp_minisocks.c|1 +
2 files changed, 2042 insertions(+)
create mode 100644 drivers/crypto/chelsi
Read FW capability. Read key area size. Dump the TLS record count.
Signed-off-by: Atul Gupta
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 32 +---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h | 7 ++
drivers/net/ethernet/chelsio/cxgb4/sge.c| 98 -
Inline TLS state, connection management. Supporting macros definition.
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chtls/chtls.h| 487
drivers/crypto/chelsio/chtls/chtls_cm.h | 202 +
2 files changed, 689 insertions(+)
create mode 100644
Define macro for TLS Key context
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chcr_algo.h | 42 +
drivers/crypto/chelsio/chcr_core.h | 55 +-
2 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/chel
Key area size in hw-config file. CPL struct for TLS request
and response. Work request for Inline TLS.
Signed-off-by: Atul Gupta
---
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 121 ++-
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 2 +
drivers/net/ethernet/chelsio/cxgb4/
Facility to register Inline TLS drivers to net/tls. Setup
TLS_FULL_HW prot to listen on offload device.
Cases handled
1. Inline TLS device exists, setup prot for TLS_FULL_HW
2. Atleast one Inline TLS exists, sets TLS_FULL_HW. If
non-inline capable device establish connection move to TLS_SW_TX
Sig
tls_device structure to register Inline TLS drivers
with net/tls
Signed-off-by: Atul Gupta
---
include/net/tls.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/net/tls.h b/include/net/tls.h
index 4913430..9bfb91f 100644
--- a/include/net/tls.h
+++ b/inclu
Signed-off-by: Atul Gupta
---
include/linux/netdev_features.h | 2 ++
net/core/ethtool.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/include/linux/netdev_features.h b/include/linux/netdev_features.h
index db84c51..aacabe2 100644
--- a/include/linux/netdev_features.h
+++ b/i
Series for Chelsio Inline TLS driver (chtls.ko)
Use tls ULP infrastructure to register chtls as Inline TLS driver.
Chtls use TCP Sockets to transmit and receive TLS record. TCP proto_ops is
extended to offload TLS record.
T6 adapter provides the following features:
-TLS record offload, T
On 02/24/2018 10:03 AM, Maciej S. Szmigiero wrote:
CCP RSA implementation uses a hardware input buffer which size depends only
on the current RSA key length. Key modulus and a message to be processed
is then copied to this buffer based on their own lengths.
Since the price for providing too long
On 02/24/2018 10:03 AM, Maciej S. Szmigiero wrote:
rsa-pkcs1pad uses a value returned from a RSA implementation max_size
callback as a size of an input buffer passed to the RSA implementation for
encrypt and sign operations.
CCP RSA implementation uses a hardware input buffer which size depends
The Inline IPSec driver does not offload csum.
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chcr_ipsec.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_ipsec.c
b/drivers/crypto/chelsio/chcr_ipsec.c
index db1e241..8e0aa3f 100644
--- a
Includes kpp_query, kpp_gen_pubkey and kpp_compute_ss.
Signed-off-by: Tudor Ambarus
---
crypto/asymmetric_keys/asymmetric_type.c | 77
include/keys/asymmetric-subtype.h| 12 +
2 files changed, 89 insertions(+)
diff --git a/crypto/asymmetric_keys/asym
Includes generation of public key and computation of shared secret.
This mostly involves offloading the calls to the crypto layer.
The crypto tfm was allocated and the private key was set when parsing
the private key. This permits us to use a single tfm whatever the
number of operation calls.
The
The ECDH private keys are expected to be encoded with the ecdh
helpers from kernel.
Use the ecdh helpers to check if the key is valid. If valid,
allocate a tfm and set the private key. There is a one-to-one
binding between the private key and the tfm. The tfm is allocated
once and used as many tim
Provide three keyctl functions that permit userspace to make use of the new
key type ops for accessing and driving asymmetric kpp keys.
(*) Query an asymmetric kpp key.
long keyctl(KEYCTL_KPP_QUERY,
key_serial_t key, struct keyctl_kpp_query *res);
Get information
Provide three new operations in the key_type struct that can be used to
provide access to kpp operations. These will be implemented for the
asymmetric key type in a later patch and may refer to a key retained in
RAM by the kernel or a key retained in crypto hardware.
int (*asym_kpp_query)(cons
This series provides keyctl access for kpp operations, including
a query function, a function to generate the public key that is
associated with the private key and a function to compute the
shared secret.
I've added a KPP ecdh parser so that you can load an ECDH private
key into the kernel. The E
On Armada 7K/8K we need to explicitly enable the register clock. This
clock is optional because not all the SoCs using this IP need it but at
least for Armada 7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT
---
Documentation/devi
clk_disable_unprepare() already checks that the clock pointer is valid.
No need to test it before calling it.
Signed-off-by: Gregory CLEMENT
---
drivers/char/hw_random/omap-rng.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/char/hw_random/omap-rng.c
b/driver
Hi,
This short series fixes the way the clocks are used for the SafeXcel
IP-76 controller embedded in the Marvell Armada 7K/8K SoCs. On these
SoCs a second one is needed in order to clock the registers. It was
not noticed until now because we relied on the bootloader and also
because the clock dri
On 28-02-2018 14:28, Stephan Mueller wrote:
> Am Mittwoch, 28. Februar 2018, 08:34:21 CET schrieb Harsh Jain:
>
> Hi Harsh,
>
>> Try with gdb. AIO(-x 10) works fine with step by step debugging. Also
>> verified by adding print in "af_alg_async_cb" for received err value.
>> Driver is sending -7
Am Mittwoch, 28. Februar 2018, 08:34:21 CET schrieb Harsh Jain:
Hi Harsh,
> Try with gdb. AIO(-x 10) works fine with step by step debugging. Also
> verified by adding print in "af_alg_async_cb" for received err value.
> Driver is sending -74 here.
I am unable to reproduce the issue. Both comma
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