[PATCH v10 crypto 10/11] chtls: Register chtls Inline TLS with net tls

Register chtls as Inline TLS driver, chtls is ULD to cxgb4. Setsockopt to program (tx/rx) keys on chip. Support AES GCM of key size 128. Support both Inline Rx and Tx. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_main.c | 577

[PATCH v10 crypto 11/11] Makefile Kconfig

Entry for Inline TLS as another driver dependent on cxgb4 and chcr Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/Kconfig| 11 +++ drivers/crypto/chelsio/Makefile | 1 + drivers/crypto/chelsio/chtls/Makefile | 4 3 files changed, 16

[PATCH v10 crypto 09/11] chtls: Inline TLS request Tx/Rx

TLS handler for record transmit and receive. Create Inline TLS work request and post to FW. Create Inline TLS record CPLs for hardware Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_io.c | 1863 +++ 1 file changed, 1863

[PATCH v10 crypto 07/11] chtls: Program the TLS Key

Initialize the space reserved for storing the TLS keys get and free the location where key is stored for the TLS connection Program the tx and rx key as received from user in struct tls12_crypto_info_aes_gcm_128 and understood by hardware. Signed-off-by: Atul Gupta ---

[PATCH v10 crypto 08/11] chtls: CPL handler definition

Exchange CPL messages with hardware to program the TLS session CPL handlers defined to process messages received from chip. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_cm.c | 2041 +++ net/ipv4/tcp_minisocks.c

[PATCH v10 crypto 05/11] cxgb4: LLD driver changes to enable TLS

Read the Inline TLS capability from firmware. Determine the area reserved for storing the keys Dump the Inline TLS tx and rx records count. Signed-off-by: Atul Gupta --- drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 32 +---

[PATCH v10 crypto 04/11] chtls: structure and macro definiton

Inline TLS state, connection management. Supporting macros definition. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls.h| 487 drivers/crypto/chelsio/chtls/chtls_cm.h | 202 + 2 files changed, 689

[PATCH v10 crypto 03/11] cxgb4: Inline TLS FW Interface

Key area size in hw-config file. CPL struct for TLS request and response. Work request for Inline TLS. Signed-off-by: Atul Gupta --- drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 121 ++- drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 2 +

[PATCH v10 crypto 06/11] chcr: Inline TLS Key Macros

Define macro for programming the TLS Key context Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chcr_algo.h | 42 + drivers/crypto/chelsio/chcr_core.h | 55 +- 2 files changed, 96 insertions(+), 1

[PATCH v10 crypto 02/11] ethtool: enable Inline TLS in HW

Ethtool option enables TLS record offload on HW, user configures the feature for netdev capable of Inline TLS. This allows user to define custom sk_prot for Inline TLS sock Signed-off-by: Atul Gupta --- include/linux/netdev_features.h | 2 ++ net/core/ethtool.c

[PATCH v10 crypto 01/11] tls: support for Inline tls record

Facility to register Inline TLS drivers to net/tls. Setup TLS_HW_RECORD prot to listen on offload device. Cases handled - Inline TLS device exists, setup prot for TLS_HW_RECORD - Atleast one Inline TLS exists, sets TLS_HW_RECORD. - If non-inline device establish connection, move to TLS_SW_TX

[PATCH v10 crypto 00/11] Chelsio Inline TLS

Series for Chelsio Inline TLS driver (chtls) Use tls ULP infrastructure to register chtls as Inline TLS driver. Chtls use TCP Sockets to transmit and receive TLS record. TCP proto is extended to offload TLS record. T6 adapter provides the following features: -TLS record offload, TLS

Re: [PATCH] crypto/ccp: Validate buffer lengths for copy operations

On 07.03.2018 18:31, Gary R Hook wrote: > The CCP driver copies data between scatter/gather lists and DMA buffers. > The length of the requested copy operation must be checked against > the available destination buffer length. > > Reported-by: Maciej S. Szmigiero >

Re: [RFC PATCH cryptodev] crypto: des3_ede_skciphers[] can be static

On Sat, Mar 03, 2018 at 04:29:46AM +0800, kbuild test robot wrote: > > Fixes: 09c0f03bf8ce ("crypto: x86/des3_ede - convert to skcipher interface") > Signed-off-by: Fengguang Wu Patch applied. Thanks. -- Email: Herbert Xu Home Page:

Re: [PATCH] crypto/ccp - Fill the result buffer only on digest, finup, and final ops

On Wed, Mar 07, 2018 at 11:37:42AM -0600, Gary R Hook wrote: > Any change to the result buffer should only happen on final, finup > and digest operations. Changes to the buffer for update, import, export, > etc, are not allowed. > > Fixes: 66d7b9f6175e ("crypto: testmgr - test misuse of result in

Re: [PATCH] Crypto:Chelsio: no csum offload for ipsec path

On Wed, Feb 28, 2018 at 11:18:08PM +0530, Atul Gupta wrote: > The Inline IPSec driver does not offload csum. > > Signed-off-by: Atul Gupta Patch applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key:

Re: [PATCH 0/2] add crypto support for TPM communication

James Bottomley wrote: > To support cryptographic communication with the TPM, we need to add > Cipher FeedBack (CFB) mode for stream encryption because this is the > mandated encryption scheme for all encrypted parameters and responses. >  Additionally, we

Re: [PATCH 1/4] crypto: omap-sham: Remove useless check for non-null request

On Thu, Mar 01, 2018 at 09:50:10PM +0100, Krzysztof Kozlowski wrote: > ahash_request 'req' argument passed by the caller > omap_sham_handle_queue() cannot be NULL here because it is obtained from > non-NULL pointer via container_of(). > > This fixes smatch warning: >

Re: [PATCH 0/2] hwrng: omap: Fix clock resource for Armada 7K/8K

On Wed, Feb 28, 2018 at 03:27:21PM +0100, Gregory CLEMENT wrote: > Hi, > > This short series fixes the way the clocks are used for the SafeXcel > IP-76 controller embedded in the Marvell Armada 7K/8K SoCs. On these > SoCs a second one is needed in order to clock the registers. It was > not

Re: [PATCH 2/2] crypto: talitos - do not perform unnecessary dma synchronisation

On Mon, Feb 26, 2018 at 05:40:06PM +0100, Christophe Leroy wrote: > req_ctx->hw_context is mainly used only by the HW. So it is not needed > to sync the HW and the CPU each time hw_context in DMA mapped. > This patch modifies the DMA mapping in order to limit synchronisation > to necessary

Re: [PATCH 0/6] crypto: omap: fixes + tweaks for omap crypto

On Tue, Feb 27, 2018 at 03:30:33PM +0200, Tero Kristo wrote: > Hi, > > This series contains a couple of fixes for LPAE data handling (patch #1/#2), > and also a few configuration patches (#3..#6.) Without the fixes, > the driver will see crashes in certain data configs, most notably when > using

Re: [PATCH 1/2] crypto: talitos - don't persistently map req_ctx->hw_context and req_ctx->buf

On Mon, Feb 26, 2018 at 05:40:04PM +0100, Christophe Leroy wrote: > Commit 49f9783b0cea ("crypto: talitos - do hw_context DMA mapping > outside the requests") introduced a persistent dma mapping of > req_ctx->hw_context > Commit 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash >

Re: [PATCH] hwrng: cavium: make two functions static

On Mon, Feb 26, 2018 at 02:51:19PM +, Colin King wrote: > From: Colin Ian King > > Functions cavium_rng_remove and cavium_rng_remove_vf are local to the > source and do not need to be in global scope, so make them static. > > Cleans up sparse warnings: >

Re: [PATCH 0/3] crypto: inside-secure - fixes for heavy load usage

On Mon, Feb 26, 2018 at 02:45:09PM +0100, Antoine Tenart wrote: > Hi Herbert, > > This series contains 3 patches aimed at fixing issues when the SafeXcel > driver is used under heavy load. The first two patches move DMA mapping > informations to per-request specific contexts and the last one

Re: [PATCH 3/4] crypto: bcm: Constify *hash_alg_name[]

On Fri, Mar 09, 2018 at 06:35:35AM -0800, Joe Perches wrote: > > and likely, as this is a global name, it should > be something like crypto_hash_alg_name crypto_ is not a good prefix here. Perhaps crypto_bcm_. Thanks, -- Email: Herbert Xu Home Page:

Re: [PATCH 3/4] crypto: bcm: Constify *hash_alg_name[]

On 27.02.2018 23:01, Hernán Gonzalez wrote: > Note: This is compile only tested. > No gain from this except some self-documenting. > > Signed-off-by: Hernán Gonzalez > --- > drivers/crypto/bcm/spu.c | 5 +++-- > drivers/crypto/bcm/spu.h | 2 +- > 2 files changed,

Re: [PATCH 3/4] crypto: bcm: Constify *hash_alg_name[]

On Fri, 2018-03-09 at 22:29 +0800, Herbert Xu wrote: > On Tue, Feb 27, 2018 at 07:01:27PM -0300, Hernán Gonzalez wrote: > > Note: This is compile only tested. > > No gain from this except some self-documenting. [] > > diff --git a/drivers/crypto/bcm/spu.c b/drivers/crypto/bcm/spu.c [] > > @@ -23,8

Re: [PATCH 3/4] crypto: bcm: Constify *hash_alg_name[]

On Tue, Feb 27, 2018 at 07:01:27PM -0300, Hernán Gonzalez wrote: > Note: This is compile only tested. > No gain from this except some self-documenting. > > Signed-off-by: Hernán Gonzalez > --- > drivers/crypto/bcm/spu.c | 5 +++-- > drivers/crypto/bcm/spu.h | 2 +- >

Re: [PATCH v2] crypto/ecc: Remove stack VLA usage

On 03/08/2018 11:57 PM, Kees Cook wrote: On the quest to remove all VLAs from the kernel[1], this switches to a pair of kmalloc regions instead of using the stack. This also moves the get_random_bytes() after all allocations (and drops the needless "nbytes" variable).

Re: [PATCH] crypto/ecc: Remove stack VLA usage

On 03/08/2018 11:55 PM, Kees Cook wrote: Looks like there are few intermediate buffers in ecc that should be zeroized as well. Can you send a patch for those? Yeah, I'll take a look. Best, ta